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參數(shù)資料
| 型號： | HMS87C1304A |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | CMOS單芯片8位微控制器 |
| 文件頁數(shù)： | 56/70頁 |
| 文件大?。?/td> | 977K |
| 代理商： | HMS87C1304A |
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HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
56
Preliminary
Jan. 2001
17. Power Saving Mode
For applications where power consumption is a critical
factor, device provides three kinds of power saving func-
tions, STOP mode, Wake-up Timer mode and internal RC-
oscillated watchdog timer mode.
The power saving function is activated by execution of
STOP instruction after setting the corresponding bit
(WAKEUP, RCWDT) of CKCTLR.
Table 17-1 shows the status of each Power Saving Mode
Note: Before executing STOP instruction, clear all in-
terrupt request flag.
Because if the interrupt re-
quest flag is set before STOP instruction, the MCU
runs as if it doesn’t perform STOP instruction, even
though the STOP instruction is completed. So insert
two lines to clear all interrupt request flags (IRQH,
IRQL) before STOP instruction as shown each ex-
ample.
17.1 Stop Mode
In the Stop mode, the on-chip oscillator is stopped. With
the clock frozen, all functions are stopped, but the on-chip
RAM and Control registers are held. The port pins out the
values held by their respective port data register, port di-
rection registers. Oscillator stops and the systems internal
operations are all held up.
The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
The program counter stop the address of the
instruction to be executed after the instruction
“STOP” which starts the STOP operating mode.
The Stop mode is activated by execution of STOP in-
struction after setting the bit WAKEUP and RCWDT
of CKCTLR to “00”. (This register should be written
by byte operation. If this register is set by bit manipu-
lation instruction, for example “set1” or “clr1” instruc-
tion, it may be undesired operation)
In the Stop mode of operation, V
DD
can be reduced to min-
imize power consumption. Care must be taken, however,
to ensure that V
DD
is not reduced before the Stop mode is
invoked, and that V
DD
is restored to its normal operating
level, before the Stop mode is terminated.
The reset should not be activated before V
DD
is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
Note:
After STOP instruction, at least two or more NOP
instruction should be written
Ex)
LDM CKCTLR
,#0
00
0_1110B
LDM IRQH
,#0
LDM IRQL
,#0
STOP
NOP
NOP
In the STOP operation, the dissipation of the power asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
Peripheral
STOP
Wake-up Timer
Internal RC-WDT
RAM
Retain
Retain
Retain
Control Registers
Retain
Retain
Retain
I/O Ports
Retain
Retain
Retain
CPU
Stop
Stop
Stop
Timer0
Stop
Operation
Stop
Oscillation
Stop
Oscillation
Stop
Prescaler
Stop
÷
2048 only
Stop
Internal RC oscillator
Stop
Stop
Oscillation
Entering Condition
CKCTLR[6,5]
00
1X
01
Power Saving Release
Source
RESET, INT0, INT1
RESET, INT0, INT1,
Timer0
RESET, INT0, INT1,
RC-WDT
Table 17-1 Power Saving Mode
Preimnary
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