參數(shù)資料
型號(hào)： HMP8190EVAL1
廠商： Intersil Corporation
英文描述： NTSC/PAL Video Encoder
中文描述： NTSC / PAL視頻編碼器
文件頁(yè)數(shù)： 22/32頁(yè)
文件大小： 227K
代理商： HMP8190EVAL1
22
Pinout
HMP8190/HMP8191
(PQFP)
TOP VIEW
6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VAA
VAA
Y
GND
VAA
GND
C
GND
VAA
GND
NTSC/PAL
GND
VAA
GND
GND
GND
P8
P9
P10
P11
P12
P13
GND
CLK2
VAA
CLK
P14
P15
VSYNC
HSYNC
FIELD
BLANK
G
S
S
N
V
R
G
N
N
N
N
N
N
S
R
N
C
F
V
P
V
G
P
P
P
P
P
P
P
C
G
G
Pin Descriptions
PIN
NAME
PIN
NUMBER
INPUT/
OUTPUT
DESCRIPTION
P0-P15
58, 55-43,
38, 37
I
Pixel Input Pins. See Table 1. Any pixel inputs not used should be connected to GND.
NC
32-27, 23,
22
I
No Connect Pins. These pins are not used. They may be left floating or may be connected
to GND.
RESV
21
I
This pin is reserved and should be connected to GND.
FIELD
34
O
FIELD Output. The field output indicates that the encoder is outputting the odd or even video
field. The polarity of FIELD is programmable.
HSYNC
35
I/O
Horizontal Sync Input/Output. As an input, this pin must be asserted during the horizontal
sync intervals. If it occurs early, the line time will be shortened. If it occurs late, the line time
will be lengthened by holding the outputs at the front porch level. As an output, it is asserted
during the horizontal sync intervals. The polarity of HSYNC is programmable. If not driven,
the circuit for this pin should include a 4-12k
pull up resistor connected to VAA.
VSYNC
36
I/O
Vertical Sync Input/Output. As an input, this pin must be asserted during the vertical sync
intervals. If it occurs early, the field time will be shortened. If it occurs late, the field time will
be lengthened by holding the outputs at the blanking level. As an output, it is asserted during
the vertical sync intervals. The polarity of VSYNC is programmable. If not driven, the circuit
for this pin should include a 4-12k
pull up resistor connected to VAA.
BLANK
33
I/O
Composite Blanking Input/Output. As an input, this pin must be asserted during the horizon-
tal and vertical blanking intervals. As an output, it is asserted during the horizontal and ver-
tical blanking intervals. The polarity of BLANK is programmable. If not driven, the circuit for
this pin should include a 4-12k
pull up resistor connected to VAA.
CLK
39
I/O
1x Pixel Clock Input/Output. As an input, this clock must be free-running and synchronous
to the clock signal on the CLK2 pin. As an output, this pin may drive a maximum of one LS
TTL load. CLK is generated by dividing CLK2 by two or four, depending on the mode. If not
driven, the circuit for this pin should include a 4-12k
pull up resistor connected to VAA.
CLK2
41
I
2x Pixel Clock Input. This clock must be a continuous, free-running clock.
HMP8190, HMP8191
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