參數(shù)資料
型號(hào)： HMP8117CNZ
廠商： Intersil
文件頁(yè)數(shù)： 42/45頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC/PAL 80PQFP
標(biāo)準(zhǔn)包裝： 66
類(lèi)型： 視頻解碼器
應(yīng)用： 視頻
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-BQFP
供應(yīng)商設(shè)備封裝： 80-QFP（14x20）
包裝： 托盤(pán)
6
FN4643.4
July 29, 2009
Input Signal Detection
If no input video signal is detected for 16 consecutive line
periods, nominal video timing is generated for the previously
detected or programmed video standard. A maskable
interrupt is provided for the condition of “Input Signal Loss”
allowing the host to enable blue field output if desired.
Vertical Sync and Field Detection
The vertical sync and field detect circuit uses a low time
counter to detect the vertical sync sequence in the video
data stream. The low time counter accumulates the low time
encountered during any sync pulse, including serration and
equalization pulses. When the low time count exceeds the
vertical sync detect threshold, VSYNC is asserted
immediately. FIELD is asserted at the same time that
VSYNC is asserted. FIELD is asserted low for odd fields and
high for even fields. Field is determined from the location in
the video line where VSYNC is detected. If VSYNC is
detected in the first half of the line, the field is odd. If VSYNC
is detected in the second half of a line, the field is even.
In the case of lost vertical sync or excessive noise that would
prevent the detection of vertical sync, the FIELD output will
continue to toggle. Lost vertical sync is declared if after 337
lines, a vertical sync period was not detected for 1 or 3
(selectable) successive fields as specified by bit 2 of the
GENLOCK CONTROL register 04H. When this occurs, the
PLLs are initialized to the acquisition state.
Y/C Separation
A composite video signal has the luma (Y) and chroma (C)
information mixed in the same video signal. The Y/C
separation process is responsible for separating the
composite video signal into these two components. The
HMP8117 utilizes a comb filter to minimize the artifacts that
are associated with the Y/C separation process.
Input Sample Rate Converter
The input sample rate converter is used to convert video data
sampled at the CLK2 rate to a virtual 4xfSC sample rate for
comb filtering and color demodulation. An interpolating filter is
used to generate the 4xfSC samples as illustrated in Figure 2.
Comb Filter
A 2-line comb filter, using a single line delay, is used to
perform part of the Y/C separation process. During S-video
operation, the Y signal bypasses the comb filter; the C signal
is processed by the comb filter since it is an integral part of
the chroma demodulator. During PAL operation, the chroma
trap filter should also be enabled for improved performance.
Since a single line store is used, the chroma will normally
have a half-line vertical offset from the luma data. This may
be eliminated, vertically aligning the chroma and luma
samples, at the expense of vertical resolution of the luma. Bit
0 of the OUTPUT FORMAT register 02H controls this option.
Chroma Demodulation
The output of the comb filter is further processed using a
patented frequency domain transform to complete the Y/C
separation and demodulate the chrominance.
Demodulation is done at a virtual 4xfSC sample rate using
the interpolated data samples to generate U and V data. The
demodulation process decimates by 2 the U/V sample rate.
Output Sample Rate Converter
The output sample rate converter converts the Y, U and V data
from a virtual 4xfSC sample rate to the desired output sample
rate (i.e., 13.5MHz). It also vertically aligns the samples based
on the horizontal sync information embedded in the digital video
data stream. The output sample rate is determined by the input
video standard and the selected rectangular/square pixel
mode. The output pixel rate is 1/2 of the CLK2 input clock
frequency. The output format is 4:2:2 for all modes except the
RGB modes which use a 4:4:4 output format.
CLK2 Input
The decoder requires a stable clock source for the CLK2
input. For best performance, use termination resistor(s) to
minimize pulse overshoot and reflections on the CLK2 input.
Since chroma demodulation uses the virtual 4xfSC, any jitter
on CLK2 will be transferred as chrominance error on the
output pixels. The CLK2 clock frequency must be one of the
valid selections from Table 1 below based on the video
standard and desired pixel mode.
The CLK2 should be derived from a stable clock source,
such as a crystal. CLK2 must have at least a
±50ppm
accuracy and at least a 60/40% duty cycle to ensure proper
TIME
INCOMING VIDEO SAMPLES
TIME
RESAMPLED VIDEO
4xfSC
FIGURE 2. SAMPLE RATE CONVERSION
TABLE 1. VIDEO STANDARD CLOCK RATE SELECTION
SUMMARY
VIDEO FORMAT
VALID CLK2
FREQUENCIES (MHz)
RECTANGULAR
PIXEL MODE
SQUARE
PIXEL MODE
(M) NTSC, (M) PAL
27.00
24.54
(B, D, G, H, I, N, NC) PAL
27.00
29.50
HMP8117
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