within the HMP8117, an I" />
參數(shù)資料
型號(hào)： HMP8117CNZ
廠商： Intersil
文件頁(yè)數(shù)： 14/45頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC/PAL 80PQFP
標(biāo)準(zhǔn)包裝： 66
類型： 視頻解碼器
應(yīng)用： 視頻
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 80-BQFP
供應(yīng)商設(shè)備封裝： 80-QFP（14x20）
包裝： 托盤
21
FN4643.4
July 29, 2009
In order to perform a read from a specific control register
within the HMP8117, an I2C bus write must first be
performed to properly setup the address register. Then an
I2C bus read can be performed to read from the desired
control register(s). As a result of needing the write cycle for a
read cycle there are actually two START conditions as
shown in Figure 19. The address register is then
auto-incremented after each byte read during the I2C read
cycle. Reserved registers return a value of 00H.
FIGURE 17. I2C TIMING DIAGRAM
SDA
SCL
tBUF
tLOW
tHIGH
tR
tF
tSU:DATA
tHD:DATA
tSU:STOP
SDA
SCL
START
CONDITION
S
1-7
ADDRESS
8
R/W
9
ACK
1-7
DATA
89
ACK
STOP
CONDITION
P
FIGURE 18. I2C SERIAL DATA FLOW
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
FROM MASTER
FROM HMP8117
0x88
DATA WRITE
DATA
0x88
DATA READ
NA = NO ACKNOWLEDGE
0x89
1000 1000 (R/W)
1000 1000
FIGURE 19. REGISTER WRITE/READ FLOW
S
CHIP ADDR
A
SUB ADDR
DATA
P
NA
CHIP ADDR
S
SUB ADDR
CHIP ADDR
S
P
A
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
A
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
HMP8117
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