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參數(shù)資料
型號： HMP8117CNZ
廠商： Intersil
文件頁數(shù)： 22/45頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC/PAL 80PQFP
標準包裝： 66
類型： 視頻解碼器
應用： 視頻
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 80-BQFP
供應商設備封裝： 80-QFP（14x20）
包裝： 托盤
29
FN4643.4
July 29, 2009
TABLE 24. INTERRUPT STATUS REGISTER
SUB ADDRESS = 10H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Genlock Loss
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to a loss of genlock.
To clear the interrupt request, a “1” must be written to this bit.
0B
6
Input Signal Loss
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to a loss of input video signal.
To clear the interrupt request, a “1” must be written to this bit.
0B
5
Closed Caption
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to new data in the closed caption data
registers. To clear the interrupt request, a “1” must be written to this bit.
0B
4
WSS Interrupt
Status
If set to “1”, this bit indicates the interrupt request was due to new data available in the WSS data
registers. To clear the interrupt request, a “1” must be written to this bit.
0B
3
Teletext Interrupt
Status
If set to “1”, this bit indicates the interrupt request was due to the detection of teletext data in the
current field. To clear the interrupt request, a “1” must be written to this bit.
0B
2
MV Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to a change in the MV Detection Status
of register 0EH. To clear the interrupt request, a “1” must be written to this bit.
0B
1
Auto Detect
Video Standard
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to the successful auto detection of a
video standard. To clear the interrupt request, a “1” must be written to this bit.
0B
0
Vertical Sync
Interrupt Status
If set to “1”, this bit indicates the interrupt request was due to the start of a new field.
To clear the interrupt request, a “1” must be written to this bit.
0B
TABLE 25. RAW VBI CONTROL REGISTER
SUB ADDRESS = 11H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-4
Reserved
0000B
3
RAW Preamble
Enable
If set to “1”, enables a four byte preamble in the RAW VBI data stream.
The preamble format is FFH, CNT1, CNT2 and 00H, where:
CNT1:
Bit 7 = even parity bar,
Bit 6 = even parity[5-0],
Bit 5 = 0,
Bit 4 = Field (0=Odd, 1=Even),
Bits 3 -0 =Linecount[8-4].
CNT2:
Bit 7 = even parity bar,
Bit 6 = even parity [5-0],
Bits 5-4 = 00
Bits 3-0 = Linecount[3-0].
0B
2
RAW VBI
All
If set to “1”, all the video lines (full field) are converted to RAW VBI data.
If set to “0”, only the lines enabled by the RAW VBI LINE MASK registers are converted to RAW
VBI data.
0B
1
RAW VBI
Even Field
If set to “1”, even field lines are converted to RAW VBI data as specified by the RAW VBI All bit
and the RAW VBI LINE MASK registers.
If set to “0”, the even field lines are excluded from the RAW VBI data stream.
0B
0
RAW VBI
Odd Field
If set to “1”, odd field lines are converted to RAW VBI data as specified by the RAW VBI All bit
and the RAW VBI LINE MASK registers.
If set to “0”, the odd field lines are excluded from the RAW VBI data stream.
0B
HMP8117
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