參數(shù)資料
型號(hào)： HMP8117
廠商： Intersil Corporation
英文描述： NTSC/PAL Video Decoder
中文描述： NTSC / PAL視頻解碼器
文件頁數(shù)： 9/45頁
文件大?。?/td> 269K
代理商： HMP8117
9
for gamma = 2.2:
for R
′
B
′
< 0.0812*31, G
′
< 0.0812*63
R = (31)((R
′
/31)/4.5)
G = (63)((G
′
/63)/4.5)
B = (31)((B
′
/31)/4.5)
for R
′
B
′
>= 0.0812*31, G
′
>= 0.0812*63
R = (31)(((R
′
/31) + 0.099)/1.099)
2.2
G = (63)(((G
′
/63) + 0.099)/1.099)
2.2
B = (31)(((B
′
/31) + 0.099)/1.099)
2.2
for gamma = 2.8:
R = (31)(R
′
/31)
2.8
G = (63)(G
′
/63)
2.8
B = (31)(B
′
/31)
2.8
Built-in Video Generation
The decoder can be configured to output a full-screen of built-in
blue, black or 75% color bar patterns. The type of pattern
generated is determined by bits 2-1 of the OUTPUT FORMAT
register 02
H
. When built-in video generation is not desired, the
bits need to be set for normal operation to pass decoded video.
If the decoder is currently locked to a video source on the
input, the output data timing will be based on the input video
source. If an input video source is not detected, internally-
generated output data timing will be used. The following
table lists the data codes output for each built-in video
pattern in YCbCr format.
Pixel Port Timing
The the timing and format of the output data and control
signals is presented in the following sections. Refer to the
section “CYCLE SLIPPING AND REAL-TIME PIXEL
JITTER” for PLL and interface considerations.
HSYNC and VSYNC Timing
The HSYNC and VSYNC output timing is VMI v1.4 compatible.
Figures 3-6 illustrate the video timing. The leading edge of
HSYNC is synchronous to the video input signal and has a
fixed latency due to internal pipeline processing. The pulse
width of the HSYNC is defined by the END HSYNC register
36
H
, where the trailing edge of HSYNC has a programmable
delay of 0-510 CLK2 cycles from the leading edge.
TheleadingedgeofVSYNCisassertedapproximatelyhalfway
through the first serration pulse of each field. An accumulator is
used to detect a low-time period within the serration pulse.
Since the leading edge of VSYNC is detected, it should not be
used for timing with respect to HSYNC or BLANK.
The trailing edge of VSYNC implements the VMI handshake
with HSYNC in order to determine field information without
using the FIELD pin. For an odd field, the trailing edge of
VSYNC is 5
±
1 CLK2 cycles after the trailing edge of the
HSYNC that follows the last equalization pulse. Refer to
Figures 3 and 5. For an even field, the trailing edge of VSYNC
is 5
±
1 CLK2 cycles after the leading edge of the HSYNC that
follows the last equalization pulse. Refer to Figures 4 and 6.
Field Timing
When field information can be determined from the input
video source, the FIELD output pin reflects the video source
field state. When field information cannot be determined
from the input video source, the FIELD output pin alternates
its state at the beginning of each field. FIELD changes state
5
±
1 CLK2 cycles before the leading edge of VSYNC.
TABLE 2. BUILT-IN VIDEO PATTERN DATA CODES
PATTERN: COLOR
Y
Cb
Cr
75% Color Bar: White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
B4
H
A2
H
83
H
70
H
54
H
41
H
23
H
10
H
4B
H
10
H
80
H
2C
H
9C
H
48
H
B8
H
64
H
D4
H
80
H
D9
H
80
H
80
H
8E
H
2C
H
3A
H
C6
H
D4
H
72
H
80
H
88
H
80
H
Blue Screen: Blue
Black Screen: Black
VIDEO
INPUT
VSYNC
FIELD
‘EVEN’ FIELD
FIGURE 3. NTSC(M) AND PAL(M) ODD FIELD TIMING
‘ODD’ FIELD
HSYNC
523
524
525
1
2
3
4
5
6
7
522
521
1
2
3
4
5
6
7
8
9
10
525
524
PAL(M) LINE#
NTSC(M) LINE#
HMP8117
相關(guān)PDF資料
PDF描述
HMP8117CN NTSC/PAL Video Decoder
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HMP8154CN NTSC/PAL Encoders
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HMP8117_07 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder
HMP8117CN 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 80PQFP,0+70C NTSC/PAL VIDEO DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
HMP8117CN96 制造商:Rochester Electronics LLC 功能描述:- Bulk
HMP8117CNZ 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 W/ANNEAL 80PQFP 0+70 DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
HMP8154 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders
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