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參數(shù)資料
| 型號(hào)： | HMP8117 |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 21/45頁 |
| 文件大?。?/td> | 269K |
| 代理商： | HMP8117 |
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21
SDA must be pulled high using external 4k
pull-up
resistors. The SA input pin determines the slave address for
the HMP8117. If the SA pin is pulled low, the address is
1000100x
B
. If the SA pin is pulled high through a 10k
pull-
up resistor, the address is 1000101x
B
. (This ‘x’ bit in the
address is the I
2
C read flag.)
Data is placed on the SDA line when the SCL line is low and
held stable when the SCL line is pulled high. Changing the
state of the SDA line while SCL is high will be interpreted as
either an I
2
C bus START or STOP condition as indicated by
Figure 18.
During I
2
C write cycles, the first data byte after the slave
address is treated as the control register sub address and is
written into the internal address register. Any remaining data
bytes sent during an I
2
C write cycle are written to the control
registers, beginning with the register specified by the
address register as given in the first byte. The address
register is then auto-incremented after each additional data
byte sent on the I
2
C bus during a write cycle. Writes to
reserved bits within registers or reserved registers are
ignored.
In order to perform a read from a specific control register
within the HMP8117, an I
2
C bus write must first be
performed to properly setup the address register. Then an
I
2
C bus read can be performed to read from the desired
control register(s). As a result of needing the write cycle for a
read cycle there are actually two START conditions as
shown in Figure 19. The address register is then auto-
incremented after each byte read during the I
2
C read cycle.
Reserved registers return a value of
00
H
.
FIGURE 17. I
2
C TIMING DIAGRAM
SDA
SCL
t
BUF
t
LOW
t
HIGH
t
R
t
F
t
SU:DATA
t
HD:DATA
tSU:STOP
SDA
SCL
START
CONDITION
S
1-7
ADDRESS
8
R/W
9
ACK
1-7
DATA
8
9
ACK
STOP
CONDITION
P
FIGURE 18. I
2
C SERIAL DATA FLOW
HMP8117
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMP8117CN | NTSC/PAL Video Decoder |
| HMP8154 | NTSC/PAL Encoders |
| HMP8154CN | NTSC/PAL Encoders |
| HMP8156A | NTSC/PAL Encoders |
| HMP8154EVAL1 | NTSC/PAL Encoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMP8117_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8117CN | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 80PQFP,0+70C NTSC/PAL VIDEO DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8117CN96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8117CNZ | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 W/ANNEAL 80PQFP 0+70 DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8154 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
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