參數(shù)資料
型號: HMP8116CN
廠商: HARRIS SEMICONDUCTOR
元件分類: 顏色信號轉(zhuǎn)換
英文描述: NTSC/PAL Video Decoder
中文描述: COLOR SIGNAL DECODER, PQFP80
文件頁數(shù): 9/43頁
文件大?。?/td> 182K
代理商: HMP8116CN
9
field state. When field information cannot be determined
from the input video source, the FIELD output pin alternates
its state at the beginning of each field. FIELD changes state
5
±
1 CLK2 cycles before the the leading edge of VSYNC.
VIDEO
INPUT
VSYNC
FIELD
‘EVEN’ FIELD
NOTE:
3. The trailing edge of VSYNC is 5
±
1 clocks after the trailing edge of HSYNC to be VMI compatible and to indicate a transition to an odd field.
FIGURE 4. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION
‘ODD’ FIELD
HSYNC
523
PAL(M)
LINE #
524
525
1
2
3
4
5
6
7
522
521
1
NTSC(M)
LINE #
2
3
4
5
6
7
8
9
10
525
524
NOTE:
4. The trailing edge of VSYNC is 5
±
1 clocks after the leading edge of HSYNC to be VMI compatible and to indicate a transition to an even field.
FIGURE 5. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION
VIDEO
INPUT
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
HSYNC
261
PAL(M)
LINE #
262
263
264
265
266
267
268
269
270
260
259
264
NTSC(M)
LINE #
265
266
267
268
269
270
271
272
273
263
262
VIDEO
INPUT
VSYNC
FIELD
‘EVEN’ FIELD
NOTE:
5. The trailing edge of VSYNC is 5
±
1 clocks after the trailing edge of HSYNC is to be VMI compatible and to indicate a transition to an odd field.
FIGURE 6. PAL(B,D,G,H,I,N,N
C
) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION
‘ODD’ FIELD
HSYNC
623
LINE #
624
625
1
2
3
4
5
6
7
622
621
HMP8116
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