參數(shù)資料
型號： HMP8116CN
廠商： HARRIS SEMICONDUCTOR
元件分類： 顏色信號轉(zhuǎn)換
英文描述： NTSC/PAL Video Decoder
中文描述： COLOR SIGNAL DECODER, PQFP80
文件頁數(shù)： 36/43頁
文件大小： 182K
代理商： HMP8116CN
36
TABLE 48. WSS_EVEN_B DATA REGISTER
SUB ADDRESS = 28
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
15-14
Reserved
00
B
13-8
Even Field
WSS Data
If even field WSS is enabled and present, this register is loaded with the second six bits
of WSS information on line 280, 283, or 336. Data written to this register is ignored.
000000
B
TABLE 49. WSS_CRC_EVEN DATA REGISTER
SUB ADDRESS = 29
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Reserved
00
B
5-0
Even Field
WSS CRC Data
If even field WSS is enabled and present during NTSC operation, this register is loaded
with the six bits of CRC information on line 283. It is always a “000000” during PAL oper-
ation. Data written to this register is ignored.
000000
B
TABLE 50. START H_BLANK LOW REGISTER
SUB ADDRESS = 30
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at
which to assert BLANK each scan line. Bit 0 is always a “0”, so the start of horizontal
blanking may only be done with two pixel resolution. The leading edge of HSYNC is count
000
H
.
4A
H
TABLE 51. START H_BLANK HIGH REGISTER
SUB ADDRESS = 31
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
15-10
Reserved
000000
B
9-8
Assert BLANK
Output Signal
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at
which to assert BLANK each scan line. The leading edge of HSYNC is count 000
H
.
11
B
TABLE 52. END H_BLANK REGISTER
SUB ADDRESS = 32
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to negate
BLANKeach scan line. Bit 0 is always a “0”, so the end of horizontal blanking may only be
done with two pixel resolution. The leading edge of HSYNC is count 000
H
.
7A
H
TABLE 53. START V_BLANK LOW REGISTER
SUB ADDRESS = 33
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. It specifies the line number to assert BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even
fields. For PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even
fields.
02
H
HMP8116
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