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參數(shù)資料
| 型號(hào)： | HM624100HCJP-10 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M High Speed SRAM (1-Mword x 4-bit) |
| 中文描述： | 4分高速SRAM（1 - Mword × 4位） |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 65K |
| 代理商： | HM624100HCJP-10 |
HM624100HC Series
4
Block Diagram
I/O1
.
.
.
I/O4
WE
CS
Input
data
control
Column I/O
Column decoder
1024-row
×
64-column
×
16-block
×
4-bit
(4,194,304 bits)
Row
decoder
OE
CS
CS
V
CC
V
SS
CS
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
(MSB)
A8 A9 A19 A17 A18 A15 A0 A2 A4 A16
(LSB)
(MSB)
(LSB)
Internal
voltage
generater
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM624100HC | Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 |
| HM624100HJP-10 | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HJP-12 | SMT CAPACITOR - 0.1 UF, 50 VOLT, 20% |
| HM624100HJP-15 | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100H | Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CFP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM624100HCJP-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM: Notes on Usage Technical Update/Device |
| HM624100HCLJP-10 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HCLJP-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM: Notes on Usage Technical Update/Device |
| HM624100HJP-10 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HJP-12 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4M High Speed SRAM (1-Mword x 4-bit) |
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