參數(shù)資料
型號: HM5425801B
廠商: Hitachi,Ltd.
英文描述: 256M SSTL_2 interface DDR SDRAM(256M SSTL_2接口 DDR 同步DRAM)
中文描述: 256M DDR SDRAM的接口SSTL_2(256M SSTL_2接口的DDR同步DRAM)的
文件頁數(shù): 20/62頁
文件大?。?/td> 1016K
代理商: HM5425801B
HM5425161B, HM5425801B, HM5425401B Series
20
Operation of the DDR SDRAM
Power-up Sequence
The following sequence is recommended for Power-up.
(1) Apply power and attempt to maintain CKE at an LVCMOS low state (all other inputs may be undefined).
Apply V
CC
before or at the same time as V
CCQ
.
Apply V
CCQ
before or at the same time as V
TT
and V
REF
.
(2) Start clock and maintain stable condition for a minimum of 200
μ
s.
(3) After the minimum 200
μ
s of stable power and clock (CLK,
CLK
), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200
cycles of clock input is required to lock the DLL after every DLL reset).
(7) Issue precharge all command for the device.*
1
(8) Issue 2 or more auto-refresh commands.*
1
(9) Issue a mode register set command to initialize device operation.
Note: 1. Sequence of (7) and (8) may be reversed.
Power-up Sequence after CKE Goes High
Command
EMRS
PALL
MRS
REF
2 cycles (min)
2 cycles (min)
200 cycles (min)
2 cycles (min)
2 cycles (min)
t
RP
t
RC
t
RC
PALL
MRS
REF
coAny
DLL enable
DLL reset
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