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| 型號(hào)： | HM5117805TT-7 |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 16 M EDO DRAM (2-Mword X 8-bit) 2 k Refresh |
| 中文描述： | 2M X 8 EDO DRAM, 70 ns, PDSO28 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-28 |
| 文件頁(yè)數(shù)： | 12/32頁(yè) |
| 文件大小： | 549K |
| 代理商： | HM5117805TT-7 |
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EO rdc
page mode mix cycle (1) and (2).
HM5117805 Series
Data Sheet E0156H10
12
Self Refresh Mode (L-version)
HM5117805L
-5
-6
-7
Parameter
RAS
pulse width (self refresh)
RAS
precharge time (self refresh)
CAS
hold time (self refresh)
Notes: 1. AC measurements assume t
T
= 2 ns.
2. An initial pause of 200 μs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
RAS
-only refresh or
CAS
-before-
RAS
refresh). If the
internal refresh counter is used, a minimum of eight
CAS
-before-
RAS
refresh cycles are required.
3. Operation with the t
RCD
(max) limit insures that t
RAC
(max) can be met, t
RCD
(max) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, then access time is
controlled exclusively by t
CAC
.
4. Operation with the t
RAD
(max) limit insures that t
RAC
(max) can be met, t
RAD
(max) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max) limit, then access time is
controlled exclusively by t
AA
.
5. Either t
OED
or t
CDD
must be satisfied.
6. Either t
DZO
or t
DZC
must be satisfied.
7. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Also, transition
times are measured between V
IH
(min) and V
IL
(max).
8. Assumes that t
RCD
≤
t
RCD
(max) and t
RAD
≤
t
RAD
(max). If t
RCD
or t
RAD
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10.Assumes that t
RCD
≥
t
RCD
(max) and t
RAD
≤
t
RAD
(max).
11.Assumes that t
RCD
≤
t
RCD
(max) and t
RAD
≥
t
RAD
(max).
12.Either t
RCH
or t
RRH
must be satisfied for a read cycles.
13.t
OFF
(max) and t
OEZ
(max) define the time at which the outputs achieve the open circuit condition and
are not referred to output voltage levels.
14.t
WCS
, t
RWD
, t
CWD
, t
AWD
and t
CPW
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
≥
t
RWD
(min),
t
CWD
≥
t
CWD
(min), and t
AWD
≥
t
AWD
(min), or t
CWD
≥
t
CWD
(min), t
AWD
≥
t
AWD
(min) and t
CPW
≥
t
CPW
(min), the
cycle is a read-modify-write and the data output will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, the condition of the data out (at access time) s
indeterminate.
15.These parameters are referred to
CAS
leading edge in early write cycles and to
WE
leading edge
in delayed write or read-modify-write cycles.
16.t
RASP
defines
RAS
pulse width in EDO page mode cycles.
17.Access time is determined by the longest among t
AA
, t
CAC
and t
CPA
.
18.In delayed write or read-modify-write cycles,
OE
must disable output buffer prior to applying data
to the device.
19.t
HPC
(min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
mode mix cycle (1), (2)), minimum value of
CAS
cycle (t
+ t
+ 2 t
) becomes greater than the
specified t
(min) value.The value of
CAS
cycle time of mixed EDO page mode is shown in EDO
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
t
RASS
t
RPS
t
CHS
100
—
100
—
100
—
μs
90
—
110
—
130
—
ns
–50
—
–50
—
–50
—
ns
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| HM5117805LTT-5 | 16 M EDO DRAM (2-Mword X 8-bit) 2 k Refresh |
| HM5117805 | 16 M EDO DRAM (2-Mword X 8-bit) 2 k Refresh |
| HM5117805LTS-5 | 16 M EDO DRAM (2-Mword X 8-bit) 2 k Refresh |
| HM5117805LTS-6 | 16 M EDO DRAM (2-Mword X 8-bit) 2 k Refresh |
| HM5117805LTS-7 | 16 M EDO DRAM (2-Mword X 8-bit) 2 k Refresh |
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