參數(shù)資料
型號: HM5112805FLTD-6
廠商: Hitachi,Ltd.
英文描述: 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
中文描述: 128M的內(nèi)存江戶(16 Mword × 8位)8K的refresh/4k刷新
文件頁數(shù): 11/34頁
文件大小: 480K
代理商: HM5112805FLTD-6
HM5112805F-6, HM5113805F-6
11
AC Characteristics
(Ta = 0 to +70C, V
CC
= 3.3 V
±
0.3 V, V
SS
= 0 V) *
1,
*
2,
*
19
Test Conditions
Input rise and fall time: 2 ns
Input pulse levels: V
IL
= 0 V, V
IH
= 3.0 V
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + C
L
(100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles
(Common parameters)
HM5112805F/HM5113805F
-6
Parameter
Symbol
Min
Max
Unit
Notes
Random read or write cycle time
RAS
precharge time
CAS
precharge time
RAS
pulse width
CAS
pulse width
t
RC
t
RP
t
CP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
OED
t
DZO
t
DZC
t
T
104
ns
40
ns
10
ns
60
10000
ns
10
10000
ns
Row address setup time
0
ns
Row address hold time
10
ns
Column address setup time
0
ns
Column address hold time
RAS
to
CAS
delay time
RAS
to column address delay time
hold time
CAS
hold time
CAS
to
RAS
precharge time
OE
to Din delay time
OE
delay time from Din
CAS
delay time from Din
10
ns
14
45
ns
3
12
30
ns
4
15
ns
40
ns
5
ns
15
ns
5
0
ns
6
0
ns
6
Transition time (rise and fall)
2
50
ns
7
相關(guān)PDF資料
PDF描述
HM5112805FTD-6 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
HM5113805F-6 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
HM5113805FLTD-6 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
HM5113805FTD-6 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
HM5112805F 128M EDO DRAM(128M 擴展數(shù)據(jù)輸出模式動態(tài)RAM)
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參數(shù)描述
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HM5112805FTD-6 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
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