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參數(shù)資料
| 型號(hào)： | HIP9011AB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Engine Knock Signal Processor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封裝： | PLASTIC, MS-013-AC, SOIC-20 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 76K |
| 代理商： | HIP9011AB |
4-5
Timing Diagrams
FIGURE 1. SPI TIMING
B7
B6
B5
B4
B3
B2
B1
B0
SI
SCK
CS
t
CSCH
t
CSCF
t
PWH
t
PWL
t
SCCH
t
SUH
t
HH
B6
INT/HOLD
t
CIH
B7
B5
B4
B3
B2
B1
B0
SO
t
CSH
TABLE 1. SPI TIMING REQUIREMENTS
SYMBOL
REQUIREMENT
TIME
t
CSCH
Minimum time from CS falling edge to SCK rising edge.
10ns
t
CSCF
Minimum time from CS falling edge to SCK falling edge.
80ns
t
PWL
Minimum time for the SCK low.
60ns
t
PWH
Minimum time for the SCK high.
60ns
t
SCCH
Minimum time from SCK falling after 8 bits to CS raising edge.
80ns
t
SUH
Minimum time from data high to falling edge of spiclk.
20ns
t
SUL
Minimum time from data low to falling edge of spiclk.
20ns
t
HH
Minimum time for data high after the falling edge of the spiclk.
10ns
t
HL
Minimum time for data low after the falling edge of the spiclk.
10ns
t
CIH
Minimum time after CS raises until INT/HOLD goes high.
8
μ
s
t
CSH
Minimum time between programming 2 internal registers.
200ns
INT/HOLD
INTOUT
t1
t2
t3
t4
FIGURE 2. INTEGRATOR TIMING
TABLE 2. INTEGRATE/HOLD TIMING REQUIREMENTS
SYMBOL
REQUIREMENT
TIME
t1
Maximum rise time of the INT/HOLD signal.
45ns
t2
Maximum time after INT/HOLD rises for INTOUT to begin to integrate.
20
μ
s
t3
Maximum fall time of INT/HOLD signal.
45ns
t4
Typical time after INT/HOLD goes low before chip goes into hold state.
20
μ
s
HIP9011
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