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參數(shù)資料
| 型號： | HIP9010 |
| 廠商： | Intersil Corporation |
| 英文描述： | Engine Knock Signal Processor |
| 中文描述： | 發(fā)動機爆震信號處理器 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 81K |
| 代理商： | HIP9010 |
4-10
The digital block diagram shows the programming flow of the
chip. An eight bit word is received at the MISO port. Data is
shifted in by the SCK clock when the chip is enabled by the
CS pin. The word is decoded by the address decoding
circuit, and the information is directed to one of 5 registers.
These registers control:
1. Reference knock filter frequency.
2. Knock filter frequency.
3. Balance control or attenuation of one channel with
respect to the other.
4. Integration time constant of the sum of the two channels.
5. One of 3 functions.
a) test conditions of the part.
b) channel select to one of two sensors.
c) channel to be attenuated.
A crystal oscillator circuit is provided. The chip requires a 4MHz
crystal to be connected across OSCIN and OSCOUT pins.
In the test mode, use the digital multiplexer to output one of
the following signals:
1. Contents of one of the five registers in the chip.
2. Inverted signal of the MOSI pin.
3. Voltage of an internal comparator used to rectify the
analog signal.
Upon power up, chip requires that the INT/HOLD pin is
toggled. If this is not done then it is important to note, that
only the first result and SPI data bytes sent after power up
will not be valid. Any subsequent chip operation will then be
performed correctly.
REFERENCE FILTER
KNOCK FILTER
BALANCE CONTROL
INTEGRATOR TIME CONSTANT
TEST/ CHANNEL SELECT ATTENUATE
D
OSCILLATOR
CIRCUIT
ADDRESS DECODER
S
MOSI
SCK
CS
MOSI
TEST
COMPARATOR OUT
(FROM RECTIFIER PHASE
DETECTOR)
MISO
OSCOUT
OSCIN
FIGURE 5. DIGITAL BLOCK DIAGRAM
TABLE 3. SPI TIMING REQUIREMENTS
DESCRIPTION
UNITS
T1 minimum time from CS falling edge to SCK falling edge.
10ns
T2 minimum time from CS falling edge to SCK rising edge.
80ns
T3 minimum time for the SCK low.
60ns
T4 minimum time for the SCK high.
60ns
T5minimumtimefromSCKriseafter8bitstoCSrisingedge.
80ns
T6 minimum time from data valid to rising edge of SCK.
60ns
T7 minimum time for data valid after the rising edge of the
SCK.
10ns
T8 minimum time after CS rises until INT/HOLD goes high.
8
μ
s
B7
B6
B5
B4
B3
B2
B1
B0
DATA IN
SCK
CS
T1
T2
T3
T4
T5
T6
T7
INT/HOLD
T8
FIGURE 6. SPI TIMING
HIP9010
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HIP9010AB | 制造商:Intersil Corporation 功能描述: |
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| HIP9011AB | 功能描述:IC SENSOR ENGINE KNOCK 20-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| HIP9011ABR4682 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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