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參數(shù)資料
| 型號： | HIP7030A2 |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | J1850 8位單片機(jī)68HC05的 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 44K |
| 代理商： | HIP7030A2 |
9-47
HIP7030A0
FIGURE 5. SIGNAL TIMING DIAGRAM (ALC = 1)
FETCH
READ (INTERNAL)
WRITE
OSCB
DS
A0-A12
CE
RD
DB
WE
FS
Functional Pin Description
This section provides a brief description of each of the pins
of the HIP7030A0 microcontroller. A more detailed discus-
sion is contained in the HIP7030A2 data sheet.
V
DD
and V
SS
(Power)
Power is supplied to the MCU using these two pins. V
DD
is
connected to the positive supply and V
SS
is connected to the
negative supply.
IRQ (Maskable Interrupt Request - Input)
The IRQ pin is negative edge-sensitive triggering. A high to
low transition on the input to the IRQ pin will produce an
interrupt.
In the event of an interrupt request, the MCU always com-
pletes the current instruction before it responds to the
request. An internal mask can be used to inhibit the MCU
from responding to IRQ interrupts.
An edge-sensitive IRQ interrupt is generated if the IRQ pin is
pulled low for at least one t
ILIH
. The occurrence of the low
going pulse is registered in a flip-flop and the IRQ interrupt
will be recognized even if the IRQ pin has returned to a high
state before the interrupt can be serviced.
Once the edge-sensitive flip-flop is cleared (it is automati-
cally cleared at the start of the interrupt service routine) the
interrupt request is removed until the IRQ pin returns to a
high level and once again goes low.
RESET (Master Reset - Input)
The HIP7030A2 contains an integrated Power-On Reset (POR)
circuit and the RESET input is therefore not required for start-
up. It can be used to reset the MCU internal state and pro-
vides for an orderly re-start of the software after initial power-
up. A low level on the RESET pin will reset the HIP7030A0.
TCAP (Timer Capture - Input)
The TCAP input controls the input capture feature for the on-
chip programmable timer system. The TCAP input is also
used as the strobe signal to the Port D strobed outputs.
TCMP (Timer Compare - Output)
The TCMP pin provides an output for the output compare
feature of the on-chip timer system.
OSCIN (Oscillator Input - Input),
OSCOUT (Oscillator Output - Output),
OSCB (Oscillator Buffered Output - Output)
OSCIN is the input and OSCOUT is the output of an inverter/
amplifier which can be used to build either a quartz crystal or
ceramic resonator based clock oscillator. Alternatively the
OSCIN input can be driven from any external clock source
which satisfies the CMOS schmitt trigger input level require-
ments of the OSCIN pin. OSCB is a squared, buffered ver-
sion of the OSCIN signal, available for driving one external
CMOS load. See Electrical Specifications of the HIP7030A2
for output drive and input level specifications.
The fundamental internal clock is derived by a divide-by-two
of the external oscillator frequency (fOSC). All other internal
clocks are also derived from the external frequency. These
clocks include the input to the 16-bit Timer, the SPI Serial
Clock (SCK), and the VPW Symbol Encoder/Decoder (SEN-
DEC).
PA0-PA7 (Port A - Input/Output)
These eight I/O lines comprise Port A. The mode (i.e. - input
or output) of each pin is software programmable. All Port A I/
O lines are configured as inputs during power-on or RESET.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7030A2M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030A2P | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030PD WAF | 制造商:Harris Corporation 功能描述: |
| HIP7038A8 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller 8K EEPROM Version |
| HIP7038A8F | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller 8K EEPROM Version |
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