- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384423 > HIP7030A2 (Intersil Corporation) FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN PDF資料下載
參數(shù)資料
9-49
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 727-9207
FAX: (407) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HIP7030A0
bus. When ALC = 0, RD is internally gated with CE, and gen-
erated in synchronization with data bus cycles. With ALC =
0, standard RAM, ROM, and EPROM devices can be directly
connected to the HIP7030A0 with no additional components.
When ALC = 1, RD is not gated by CE and is produced t
CYC
cycle (i.e. 100ns with a 10MHz clock) ahead of data bus
transitions of the HIP7030A0’s machine cycle.
WE (Write Enable - Output)
Write Enable is an active low output pulse for use in writing
data to external RAM memory. A low level indicates valid
data on the data bus. WE is internally gated with CE for writ-
ing to external memory. Since, in most systems, external
memory is substituting for mask programmed ROM, WE is
frequently not used.
DS (Data Strobe - Output)
The Data Strobe output provides a pulse when address and
data are valid. DS can be used to transfer data to or from a
peripheral or memory and occurs every cycle and is also
used for synchronizing development tools to the oscillator
clock. DS is a continuous signal at f
OSC
÷
2, except when the
Emulator is in the WAIT or STOP mode. See the timing dia-
grams in the
Electrical Specifications
section for more
details.
FS (Fetch Status - Output)
The FS output signal goes true to indicate an opcode fetch
cycle is in progress. When ALC = 0, FS will be coincident
with the data transfer of the fetch. When ALC = 1, FS is pro-
duced t
CYC
cycle (i.e. 100ns with a 10MHz clock) ahead of
data bus transitions of the HIP7030A0’s machine cycle. See
the timing diagrams in the
Electrical Specifications
section
for more details.
Watchdog Status Register
When ALC is high, the HIP7030A0’s Watchdog Status Reg-
ister (WSR - location $1E) provides the ability to selectively
enable and disable the Watchdog Timer logic of the
HIP7030A0.
The user of a development tool should be cautioned against
accidently clearing the WDE bit of this register during final
code prove-out. During initial code development the user
may want to intentionally clear this bit to eliminate the need
to insert watchdog handling routines. The clearing of the bit
must be done following every reset.
Reset presets the WDE bit of the WSR to enable the Watch-
dog Timer.
Bit 7,6,5,4,3,2 - Unused
Bit 1 - WDE
When WDE (WatchDog Enable) is low, the Watchdog Timer is
disabled. When ALC is high, WDE is forced high by any reset.
The WDE bit should normally be cleared when servicing a
breakpoint (if OSCIN is being clocked), to avoid a Watchdog
Reset while interrogating the CPU.
The WDE bit controls the Watchdog Reset, but it doesn’t
inhibit the Watchdog Timer from advancing. Prior to re-
enabling the WDE bit, the Watchdog Timer should normally
be reset by writing $55, $AA to the Watchdog Reset Register
(WDRR, location $1D). This implies that each breakpoint
should generate a Watchdog Reset. To verify proper watch-
dog action the user should run final code with no breaks. In
some cases the number of CPU cycles utilized in the break
may be low enough to allow the watchdog to run without caus-
ing premature watchdog timeouts.
Bit 0 - WDF
The WatchDog flag (WDF), is set when a Watchdog timeout
causes a COP Reset. This flag is used to distinguish a Slow
Clock Detect from a Watchdog Timeout in the COP Reset ser-
vice routine.
Writing a 0 to the Watchdog Reset Register (WDRR, location
$1D) clears the WDF flag. WDF is cleared by Power-on
Reset, but unaffected by all other types of resets. For this rea-
son, WDF should normally be cleared (by writing a 0 to the
WDRR) following each read of the WSR.
7
6
5
4
3
2
1
0
-
-
-
-
-
-
WDE
WDF
WATCHDOG STATUS REGISTER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP7030A2M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2P | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP9010 | Engine Knock Signal Processor |
| HIP9010AB | Engine Knock Signal Processor |
| HIP9011ABZ | Engine Knock Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7030A2M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030A2P | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030PD WAF | 制造商:Harris Corporation 功能描述: |
| HIP7038A8 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller 8K EEPROM Version |
| HIP7038A8F | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller 8K EEPROM Version |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。