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參數(shù)資料
| 型號： | HIP7020 |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | J1850總線收發(fā)器，多重布線系統(tǒng) |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 81K |
| 代理商： | HIP7020 |
5
HIP7020 Signal Interface
The HIP7020 is a member of the Intersil family of low cost
multiplexed wiring ICs. As a Bus Transceiver IC, it interfaces
the module and system control logic to the vehicle signal bus
wiring. The integrated functions of the Bus Transceiver serve
as an interface for a “Class B” multiplexed communications
network. The TX digital interface is designed to accept
CMOS/TTL logic levels and convert them to the appropriate
J1850 analog serial data levels. This is accomplished using
an internally generated reference waveform and voltage
driver with a controlled current source to supply an analog
signal output to the J1850 bus load of 500
(typical).
Because of the special wave shaping used to control the
J1850 bus waveform, it is regarded as an analog signal.
In the receive mode the incoming bus analog signals are input
to the receiver at the BUS IN terminal. The bus data is
converted to logic information by comparing it to an on-chip
reference voltage. The received signal is provided as digital
output from an open collector transistor driver at the
RX output.
In the transmit mode a CMOS/TTL digital signal is received
at the TX input. It is then rise and fall time controlled, wave
shaped and level adjusted. A voltage controlled current
driver circuit transmits the signal from the BUS OUT terminal
to the J1850 Bus with current limiting protection.
Functional Blocks
The Bus Transceiver IC functional blocks, as shown in the
Block Diagram, are as follows:
TX BUF (Transmit Input Buffer Interface)
The TX Buffer input function is a data interface to the wave-
shaper reference circuit. The CMOS/TTL logic levels to be
transmitted are input to the TX pin.
Test Circuits
FIGURE 3. LOSS OF GROUND LEAKAGE TEST CIRCUIT
FIGURE 4. ELECTRICAL SPECIFICATION TEST CIRCUIT
0.1
μ
F
BUS OUT
BUS IN
GND
BATT
RX
TX
R/F
LB EN
V
BATT
10
15K
500
0.01
μ
F
SW
10K
5.1V
0.1
μ
F
100
510
μ
A
56.2K
±
1%
TRANSMIT WAVEFORM
PROCESSING/SHAPING
VOLTAGE TO
CURRENT
CONVERTER
FILTER
TX
RX
BUS OUT
R
E
I
STX
BUS IN
R
S
R
F
15K
BATT
5V
V
REF
MODE SW
SWITCH SHOWN
IN NORMAL MODE
Q1
I
SLB
LB EN
R
D
5K
LOOP-BACK
I
BO
V
BO
R/F
V
TX
LOW = 0V
V
TX
HIGH = 5V
56.2K
±
1%
BUS RECEIVER AND
VOLTAGE COMPARATOR
10
R
BS
= 500
TO 1500
τ
= R
BS
C
BS
5
μ
s
V
BATT
C
BS
R
BS
GND
HIP7020
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP7020AB | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020AP | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A0 | J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2 | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7020 DIE | 制造商:Harris Corporation 功能描述: |
| HIP7020AB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
| HIP7020AP | 制造商:Harris Corporation 功能描述: |
| HIP7030A0 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
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