參數(shù)資料
型號(hào)： HIP7020
廠商： Intersil Corporation
元件分類： FPGA
英文描述： FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述： J1850總線收發(fā)器，多重布線系統(tǒng)
文件頁(yè)數(shù)： 3/11頁(yè)
文件大?。?/td> 81K
代理商： HIP7020
3
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
BATT
. . . . . . . . . . . . . . . . . . . . . . . . . -20V to +24V
Short Term Supply Voltage, V
BATT
, 1s Max. (Note 2) . . . . . . . +35V
J1850 Bus Input Voltage, V
BUS IN
. . . . . . . . . . . . . . . . . . . . . .
±
20V
J1850 Bus Load Current, I
BO
. . . . . . . . . . . . . . . . . . . . .Self-Limiting
TX Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
RX Logic Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Load Dump (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
BUS Transient Susceptibility . . . . . . . . . . . . . . . . . . . . . . . (Note 3)
ESD:
BUS OUT, BATTERY Pins, (Air Gap, Note 4) . . . . . .
±
9kV
BUS OUT, BATTERY Pins, (Direct, Note 4) . . . . .
±
4.5kV
All Other Pins (Direct, Note 4) . . . . . . . . . . . . . . . . . .
±
2kV
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 125
o
C
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-40
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
120
160
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Fault capability of the J1850 Bus Transceiver includes reverse battery, load dump and latch-up tolerance to
±
200mA on any terminal. The
Short Term Power Supply Voltage capability is 35V for a maximum of 1s. Continued operation at this voltage may cause thermal shutdown.
3. Transient Susceptibility Bus and Battery Pins Per SAE J1113, Aug 1987, Figures 7 Test Pulses 1, 2, 3A and 3B at -50V, +100V and
±
200V
respectively.
4. ESD Conditions - SAE J1113; Aug 1987.
BUS OUT & BATTERY Pins: Air Gap and Direct Contact Discharge; R = 2k
, C = 150pF
All Other Pins: Direct Contact Discharge; R = 1.5k
, C = 100pF
Electrical Specifications
9.0V
≤
V
BATT
≤
16V; R
S
= 56.2k
±
1%; except as noted, R
BS
= 500
to 1500
and
τ
= R
BS
C
BS
= 5
μ
s.
All voltages are measured with respect to ground and the T
A
Range of -40
o
C to 125
o
C shall not be
exceeded during test unless otherwise specified. For test detail, refer to the Block Diagram, Figures 3
and 4 Test Circuits and Figures 5 and 6 Waveforms.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Idle Supply Current
I
BATT
BUS OUT Open; No Bus Signal;
V
BATT
= 12.6V; V
TX
Low
90
200
350
μ
A
Operating Voltage Range
V
BATT
(Note 5)
6
-
24
V
Supply Current,
BUS OUT Short to GND
I
BATT(SG)
BUS OUT Short to GND, V
TX
High
20
-
50
mA
Supply Current,
BUS OUT Short to BATT
I
BATT(SB)
BUS OUT to V
BATT
; I
BO
= 0 mA
V
TX
High
2
-
8
mA
V
TX
Low
90
-
350
μ
A
Thermal Shutdown Temperature
T
SD
(Note 6)
150
-
170
o
C
Thermal Shutdown Hysteresis
T
SDHYS
(Note 6)
5
10
15
o
C
TX CMOS/TTL INPUT WITH/PULL DOWN
Input Bias Current, TX
I
TX
V
TX
= 7V; (Note 7)
20
-
38
μ
A
Input Low Voltage
V
IL
-
-
0.8
V
Input High Voltage
V
IH
2.0
-
-
V
Input Capacitance
C
TX
2
-
5
pF
BUS OUT
BUS OUT High Voltage
V
BOH
V
TX
High
6.6
-
8.5
V
BUS OUT Low Voltage
V
BOL
Bus Load, R
BS
= 1.5k
; V
TX
Low
-
-
0.1
V
BUS OUT Voltage, Low Battery
V
BOH(PSL)
6V
≤
V
BATT
<
9V; V
TX
High
Note
13
-
8.5
V
Source Current, Bus Low
I
BO_LIMIT
-20V
≤
V
BUS OUT
<
[V
BOH
(Measured) - 0.8V];
V
TX
High
-20
-
-42
mA
BUS OUT During LOOPBACK
V
LOOPBACK
LB EN Low, V
TX
High
-
-
1
V
HIP7020
相關(guān)PDF資料
PDF描述
HIP7020AB FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP7020AP FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP7030A0 J1850 8-Bit 68HC05 Microcontroller Emulator Version
HIP7030A0M FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP7030A2 FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HIP7020 DIE 制造商:Harris Corporation 功能描述:
HIP7020AB 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems
HIP7020AP 制造商:Harris Corporation 功能描述:
HIP7030A0 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version
HIP7030A0M 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*