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參數(shù)資料
| 型號： | HIP7020 |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | J1850總線收發(fā)器，多重布線系統(tǒng) |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 81K |
| 代理商： | HIP7020 |
2
Block Diagram
Applications
The circuit of Figure 1 illustrates the essential elements of
the J1850 Bus Transceiver in a normal application. For nor-
mal J1850 applications, a Bus Transceiver is used at each
system node. The Electrical Specifications Table also refers
to the peripheral components shown in Figure 1 and the
Block Diagram for the HIP7020 Bus Transceiver.
NOTE: The R/F bias resistor, R
S
, should be located as close as
possible to the IC to minimize noise coupling to the R/F
pin. The ground connection of R
S
must be made directly
to the GND pin of the IC with no other current flowing in
the connecting line to prevent system ground currents
from affecting the rise/fall time control of the Wave
Shaper. The R
S
resistor value is typically specified as 1%
tolerance. If an R/F bypass capacitor is used to filter
noise, the value should be 100pF or less. For effective
noise filtering, the R/F bypass capacitor should be con-
nected direct from the R/F pin to the GND pin and should
not carry current from other sources.
Figure 2 illustrates some of the typical J1850 System
Configurations that utilize the HIP7020 Bus Transceiver.
Refer to the HIP7010 and HIP7030A2 Data Sheets for
further information on J1850 System Configuration detail.
TX
BUF
WAVE
SHAPER
WAVE
SHAPED
VOLT. REF
VOLTAGE TO
CURRENT
CONVERTER
FILTER
BUS RCVR AND
VOLT. COMP.
RX
BUF
TX
RX
BUS OUT
I
STX
BUS IN
R
F
BATT
V
CC
V
REF
LOOP-BACK
MODE SW
OVER-
TEMP SW
V+
HIP7020
Q1
I
SLB
LB EN
R
D
DIAGNOSTIC
LEVEL
SHIFTER
I
BO
SWITCH SHOWN IN
LOOP-BACK MODE
V
BO
R
E
R/F
TIME
GND
R
S
R/F TIME
0.01
μ
F
C1
M1
(NOTE)
CONTROLLER
BUS OUT
BUS IN
BATT
GND
R
F
15K
R
BS
C
BS
R
S
J1850 BUS
RX
TX
J1850 BUS
TRANSCEIVER
R/F
LB EN
MOV
R
E
10
56.2K
HIP7030A2
R
BS
= 500
TO 1500
τ
= R
BS
C
BS
5
μ
s
NOTE: MOV, M1 represents central protection, normally on the
alternator and with a typical value in the range of 27V to 40V.
FIGURE 1. TYPICAL APPLICATION CIRCUIT DIAGRAM
μ
C
HOST
HIP7010
BYTE LEVEL
INTERFACE
CIRCUIT
HIP7020
BUS
TRANSCEIVER
μ
C
HOST
HIP7030A2
μ
C
HIP7020
BUS
TRANSCEIVER
HIP7020
BUS
TRANSCEIVER
HIP7030A2
μ
C
J
FIGURE 2. TYPICAL J1850 SYSTEM CONFIGURATIONS
HIP7020
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP7020AB | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020AP | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A0 | J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2 | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7020 DIE | 制造商:Harris Corporation 功能描述: |
| HIP7020AB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
| HIP7020AP | 制造商:Harris Corporation 功能描述: |
| HIP7030A0 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
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