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參數(shù)資料
| 型號： | HIP4086AP |
| 廠商： | INTERSIL CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | 40000 SYSTEM GATE LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 1.1 A HALF BRDG BASED MOSFET DRIVER, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 75K |
| 代理商： | HIP4086AP |
4
HIP4086
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
Voltage on xHS . . . . . . . . . -6V (Transient) to 85V (-40
o
C to 150
o
C)
Voltage on xHB . . . . . . . . . . . . . . . . . . . . V
xHS
-0.3V to V
xHS
+V
DD
Voltage on xLO . . . . . . . . . . . . . . . . . . . . . V
SS
-0.3V to V
DD
+0.3V
Voltage on xHO . . . . . . . . . . . . . . . . . . . .V
xHS
-0.3V to V
xHB
+0.3V
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Operating Conditions
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . .+7V to +15V
Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
xHS
+ V
DD
Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 80V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . -40
o
C to 125
o
C
Junction Temperature Range. . . . . . . . . . . . . . . . . . -40
o
C to 150
o
C
Thermal Resistance (Typical, Note 1)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Storage Temperature Range. . . . . . . . . . -65
o
C to 150
o
C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
75
70
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. All voltages are relative to V
SS
unless otherwise specified.
3. x = A, B and C. For example, xHS refers to AHS, BHS and CHS.
Electrical Specifications
V
DD
= V
xHB
= 12V, V
SS
= V
xHS
= 0V, R
DEL
= 20K, R
UV
=
∞
, Gate Capacitance (C
GATE
) = 1000pF
PARAMETER
TEST CONDITIONS
T
J
= 25
o
C
T
J
= -40
o
C TO
150
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION
V
DD
Quiescent Current
xHI = 5V, xLI = 5V
2.7
3.4
4.2
2.1
4.3
mA
V
DD
Operating Current
f = 20kHz, 50% Duty Cycle
6.3
8.25
10.5
5
11
mA
xHB On Quiescent Current
xHI = 0V
-
40
80
-
100
μ
A
xHB Off Quiescent Current
xHI = V
DD
0.6
0.8
1.3
0.5
1.4
mA
xHB Operating Current
f = 20kHz, 50% Duty Cycle
0.7
0.9
1.3
-
2.0
mA
Qpump Output Voltage
No Load
11.5
12.5
14
10.5
14.5
V
Qpump Output Current
V
xHS
= 12V, V
xHB
= 22V
50
100
130
-
140
μ
A
xHB, xHS Leakage Current
V
xHS
= 80V, V
xHB
= 93V
R
UV
open
R
UV
open
7
24
45
-
50
μ
A
V
DD
Rising Undervoltage Threshold
6.2
7.1
8.0
6.1
8.1
V
V
DD
Falling Undervoltage Threshold
5.75
6.6
7.5
5.6
7.6
V
Minimum Undervoltage Threshold
R
UV
= V
DD
5
6.2
6.8
4.9
6.9
V
INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS
Low Level Input Voltage
-
-
1.0
-
0.8
V
High Level Input Voltage
2.5
-
-
2.7
-
V
Input Voltage Hysteresis
-
35
-
-
-
mV
Low Level Input Current
V
IN
= 0V
60
100
135
55
140
μ
A
High Level Input Current
V
IN
= 5V
-1
-
+1
-10
+10
μ
A
GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, AHO, BHO, AND CHO
Low Level Output Voltage (V
OUT
- V
SS
)
I
SINKING
= 30mA
-
100
-
-
200
mV
Peak Turn-On Current
V
OUT
= 0V
0.3
0.5
0.7
-
1.0
A
Peak Turn-Off Current
V
OUT
= 12V
0.7
1.1
1.5
0.5
1.7
A
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