參數(shù)資料
型號: HIP4086AP
廠商: INTERSIL CORP
元件分類: 功率晶體管
英文描述: 40000 SYSTEM GATE LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN
中文描述: 1.1 A HALF BRDG BASED MOSFET DRIVER, PDIP24
封裝: PLASTIC, DIP-24
文件頁數(shù): 3/9頁
文件大?。?/td> 75K
代理商: HIP4086AP
3
HIP4086
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
16
1
13
AHB
BHB
CHB
(xHB)
High-Side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each. Connect
cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin.
5
2
12
AHI
BHI
CHI
(xHI)
High-Side Logic Level Inputs. Logic at these three pins controls the three high side output drivers, AHO (Pin
17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI is high, xHO is low. Unless the
dead time is disabled by connecting RDEL (Pin 7) to ground, the low side input of each phase will override the
corresponding high side input on that phase - see Truth Table on previous page. If RDEL is tied to ground,
dead time is disabled and the outputs follow the inputs. Care must be taken to avoid shoot-through in this ap-
plication. DIS (Pin 10) also overrides the high side inputs. xHI can be driven by signal levels of 0V to 15V (no
greater than V
DD
). An internal 100
μ
A pull-up to V
DD
will hold each xHI high if the pins are not driven.
4
3
11
ALI
BLI
CLI
(xLI)
Low-Side Logic Level Inputs. Logic at these three pins controls the three low side output drivers ALO (Pin 21),
BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the lower inputs control both xLO and
xHO drivers, with the dead time set by the resistor at RDEL (Pin 7). DIS (Pin 10) high level input overrides xLI,
forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than V
DD
). An internal 100
μ
A
pull-up to V
DD
will hold xLI high if these pins are not driven.
6
V
SS
Ground. Connect the sources of the Low-Side power MOSFETs to this pin.
7
RDEL
Dead Time Setting. Connect a resistor from this pin to V
DD
to set timing current that defines the dead time
between drivers - see Figure 15. All drivers turn-off with no adjustable delay, so the RDEL resistor guarantees
no shoot-through by delaying the turn-on of all drivers. When RDEL is tied to V
SS
, both upper and lowers can
be commanded on simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1
μ
F
or smaller may be connected between RDEL and V
SS
.
8
UVLO
Undervoltage Setting. A resistor can be connected between this pin and V
SS
to program the undervoltage set
point, see Figure 16. With this pin not connected, the undervoltage disable is typically 6.6V. When this pin is
tied to V
DD
, the undervoltage disable is typically 6.2V.
9
RFSH
Refresh Pulse Setting. An external capacitor can be connected from this pin to V
SS
to increase the length of
the start up refresh pulse - see Figure 14. If this pin is not connected, the refresh pulse is typically 1.5
μ
s.
10
DIS
Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides all other inputs.
With DIS low, the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 15V
(no greater than V
DD
). An internal 100
μ
A pull-up to V
DD
will hold DIS high if this pin is not driven.
17
24
14
AHO
BHO
CHO
(xHO)
High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase.
15
23
15
AHS
BHS
CHS
(xHS)
High-Side Source Connection. Connect the sources of the High-Side power MOSFETs to these pins. The neg-
ative side of the bootstrap capacitors should also be connected to these pins.
20
V
DD
Positive Supply. Decouple this pin to V
SS
(Pin 6).
21
22
19
ALO
BLO
CLO
(xLO)
Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins.
NOTE:
x = A, B and C.
相關(guān)PDF資料
PDF描述
HIP5020 High-efficiency, Buck Converter Controller(高效電源控制器)
HIP5020DB FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP5060 ()
HIP5061 FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP5061DS FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HIP4086APZ 功能描述:功率驅(qū)動器IC 80V 1.25A 3 PHS FL W V DRVR RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時間: 下降時間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
HIP4086DEMO1Z 制造商:Intersil Corporation 功能描述:DEMO BOARD 1 - 24LD SOIC - ROHS COMPLIANT - Bulk 制造商:Intersil Corporation 功能描述:BOARD EVAL FOR HIP4086
HIP4086EVAL 功能描述:EVALUATION BOARD GP HIP4086 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 主要目的:電源管理,電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板
HIP5010 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:7V, 17A SynchroFET⑩ Complementary Drive Synchronous Half-Bridge
HIP5010IB 制造商:Rochester Electronics LLC 功能描述:- Bulk