
5
HIP4020
Application
The HIP4020 is designed to detect load current feedback from
sampling resistors of low value in the source connections of the
output drivers to V
DD
, V
SSA
and V
SSB
(See Figure 1). When the
sink or source current at OUTA or OUTB exceeds the preset
OC (Over-Current) limiting value of 550mA typical, the current
is held at the limiting value. If the OT (Over-Temperature) Shut-
down Protection limit is exceeded, temperature sensing BiMOS
circuits limit the junction temperature to 150
o
C typical.
The circuit of Figure 1 shows the Full H-Switch in a small motor-
drive application. The left (A) and right (B) H-Switch’s are con-
trolled from the A and B inputs via the A and B CONTROL
LOGIC to the MOS output transistors Q1, Q2, Q3 and Q4. The
circuit is intended to safely start, stop, and control rotational
direction for a motor requiring no more than 0.5A of supply cur-
rent. The stop function includes a Dynamic Braking feature.
With the ENABLE Inputs Low, the MOS transistors Q1 and Q3
are OFF; which cuts-off supply current to OUTA and OUTB.
With the BRAKE terminal Low and ENABLE Inputs High, either
Q1 and Q4 or Q3 and Q2 will be driven into conduction by the
DIRECTION Input Control terminal. The MOS output transistor
pair chosen for conduction is determined by the logic level
applied to the DIRECTION control; resulting in either clockwise
(CW) or counter-clockwise (CCW) shaft rotation.
When the BRAKE terminal is switched high (while holding
the ENABLE input high), the gates of both Q2 and Q4 are
driven high. Current flowing through Q2 (from the motor ter-
minal OUTA) at the moment of Dynamic Braking will con-
tinue to flow through Q2 to the V
SSA
and V
SSB
external
connection, and then continue through diode D4 to the motor
terminal OUTB. As such, the resistance of the motor winding
(and the series-connected path) dissipates the kinetic
energy stored in the system. Reversing rotation, current
flowing through Q4 (from the motor terminal OUTB), at the
moment of Dynamic Braking, would continue to flow through
Q4 to the V
SSB
and V
SSA
tie, and then continue through
diode D2 to the motor terminal OUTA, to dissipate the stored
kinetic energy as previously described.
Where V
DD
to V
SS
are the Power Supply reference terminals
for the Control Logic, the lowest practical supply voltage for
proper logic control should be no less than 2.0V. The V
SSA
and V
SSB
terminals are separate and independent from V
SS
and may be more negative than the V
SS
ground reference
terminal. However, the maximum supply level from V
DD
to
V
SSA
or V
SSB
must not be greater than the Absolute Maxi-
mum Supply Voltage rating.
Terminals A1, B1, A2, B2, ENA and ENB are internally con-
nected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge.
(See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have
CD74HCT4000 Logic Interface Protection and Level Con-
verters for TTL or CMOS Input Logic. These inputs are
designed to typically provide ESD protection up to 2kV. How-
ever, these devices are sensitive to electrostatic discharge.
Proper I.C. handling procedures should be followed.
FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION
INPUT
LEVEL
CONV.
V
DD
FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
A1
A2
ENA
(DIR)
(BRAKE)
(ENABLE)
OT AND OC
PROTECT
N-DR
LIMIT
P-DR
LIMIT
Q2
D2
Q1
D1
V
DD
V
SSA
OUTA
B1
B2
ENB
(DIR)
(BRAKE)
(ENABLE)
OT AND OC
PROTECT
N-DR
LIMIT
P-DR
LIMIT
Q4
D4
Q3
D3
V
DD
V
SSB
OUTB