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參數(shù)資料
| 型號(hào)： | HI3338KIBZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | 8-Bit, CMOS R2R D/A Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.02 us SETTLING TIME, 8-BIT DAC, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, MS-013-AA, SOIC-16 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 222K |
| 代理商： | HI3338KIBZ |
4
SUPPLY VOLTAGE
Static I
DD
or I
EE
LE = Low, D0 - D7 = High
-
100
220
μ
A
LE = Low, D0 - D7 = Low
-
-
100
μ
A
Dynamic I
DD
or I
EE
V
OUT
= 10MHz, 0V to 5V Square Wave
-
20
-
mA
Dynamic I
DD
or I
EE
V
OUT
= 10MHz,
±
2.5V Square Wave
-
25
-
mA
V
DD
Rejection
50kHz Sine Wave Applied
-
3
-
mV/V
V
EE
Rejection
50kHz Sine Wave Applied
-
1
-
mV/V
DIGITAL INPUTS
D0 - D7, LE, COMP
High Level Input Voltage
Note 1
2
-
-
V
Low Level Input Voltage
Note 1
-
-
0.8
V
Leakage Current
-
±
1
±
5
μ
A
Capacitance
-
5
-
pF
TEMPERATURE COEFFICIENTS
Output Impedance
-
200
-
ppm/×
o
C
NOTE:
1. Parameter not tested, but guaranteed by design or characterization.
Electrical Specifications
T
A
= 25
o
C, V
DD
= 5V, V
REF
+ = 4.608V, V
SS
= V
EE
= V
REF
- = GND, LE clocked at 20MHz, R
L
≥
1M
,
Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Timing Diagrams
FIGURE 1. DATA TO LATCH ENABLE TIMING
FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING
INPUT DATA
LATCH
ENABLE
t
SU1
t
SU2
t
W
t
H
LATCHED
LATCHED
DATA
FEEDTHROUGH
t
D1
t
D2
t
r
t
S
1
/
2
LSB
1
/
2
LSB
90%
10%
INPUT
DATA
LATCH
ENABLE
OUTPUT
VOLTAGE
HI3338
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