參數(shù)資料
型號： HI3338KIBZ
廠商： INTERSIL CORP
元件分類： DAC
英文描述： 8-Bit, CMOS R2R D/A Converter
中文描述： PARALLEL, 8 BITS INPUT LOADING, 0.02 us SETTLING TIME, 8-BIT DAC, PDSO16
封裝： LEAD FREE, PLASTIC, MS-013-AA, SOIC-16
文件頁數(shù)： 3/9頁
文件大?。?/td> 222K
代理商： HI3338KIBZ
3
Absolute Maximum Ratings
Thermal Information
DC Supply-Voltage Range. . . . . . . . . . . . . . . . . . . . . . .-0.5V to +8V
(V
DD
- V
SS
or V
DD
- V
EE
, Whichever Is Greater)
Input Voltage Range
Digital Inputs (LE, COMP D0 - D7). . . . V
SS
- 0.5V to V
DD
+ 0.5V
Analog Pins (V
REF
+, V
REF
-, V
OUT
) . . . .V
DD
- 8V to V
DD
+ 0.5V
DC Input Current
Digital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . .
±
20mA
Recommended Supply Voltage Range . . . . . . . . . . . . . 4.5V to 7.5V
Operating Conditions
HI3338KIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range, T
STG
. . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(Lead Tips Only)
θ
JA
(
o
C/W)
100
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
T
A
= 25
o
C, V
DD
= 5V, V
REF
+ = 4.608V, V
SS
= V
EE
= V
REF
- = GND, LE clocked at 20MHz, R
L
≥
1M
,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
8
-
-
Bits
Integral Linearity Error
See Figure 4
-
-
±
0.75
LSB
Differential Linearity Error
See Figure 4
-
-
±
0.5
LSB
Gain Error
Input Code = FF
HEX
, See Figure 3
-
-
±
0.5
LSB
Offset Error
Input Code = 00
HEX
, See Figure 3
-
-
±
0.25
LSB
DIGITAL INPUT TIMING
Update Rate
To Maintain
1
/
2
LSB Settling
DC
50
-
MHz
Update Rate
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
DC
20
-
MHz
Set Up Time t
SU1
For Low Glitch
-
-2
-
ns
Set Up Time t
SU2
For Data Store
-
8
-
ns
Hold Time t
H
For Data Store
-
5
-
ns
Latch Pulse Width t
W
For Data Store
-
5
-
ns
Latch Pulse Width t
W
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
-
25
-
ns
OUTPUT PARAMETERS
R
L
Adjusted for 1V
P-P
Output
Output Delay t
D1
From LE Edge
-
25
-
ns
Output Delay t
D2
From Data Changing
-
22
-
ns
Rise Time t
r
10% to 90% of Output
-
4
-
ns
Settling Time t
S
10% to Settling to
1
/
2
LSB
-
20
-
ns
Output Impedance
V
REF
+ = 6V, V
DD
= 6V
120
160
200
Glitch Area
-
150
-
pV-s
Glitch Area
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
-
250
-
pV-s
REFERENCE VOLTAGE
V
REF
+ Range
(+) Full Scale (Note 1)
V
REF
- + 3
-
V
DD
V
V
REF
- Range
(-) Full Scale (Note 1)
V
EE
-
V
REF
+ - 3
V
V
REF
+ Input Current
V
REF
+ = 6V, V
DD
= 6V
-
40
50
mA
HI3338
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