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參數(shù)資料
| 型號(hào)： | HI3-DAC80V-5 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | CONV D/A 12BIT OUTPUT AMP 24PDIP |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 設(shè)置時(shí)間： | 1.5µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 75°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 667k |
5
Denitions of Specications
Digital Inputs
The Hl-DAC80V accepts digital input codes in
complementary binary, complementary offset binary, and
complementary two’s complement binary.
Settling Time
That interval between application of a digital step input, and
nal entry of the analog output within a specied window
about the settled value. Intersil Corporation usually species
a unipolar 10V full scale step, to be measured from 50% of
the input digital transition, and a window of
±1/2 LSB about
the nal value. The device output is then rated according to
the worst (longest settling) case: low to high, or high to low.
In a 12-bit system
±1/2 LSB = ±0.012% of FSR.
Thermal Drift
Thermal drift is based on measurements at 25oC, at high
(TH) and low (TL) temperatures. Drift calculations are made
for the high (TH -25
oC) and low (25oC-T
L) ranges, and the
larger of the two values is given as a specication
representing worst case drift.
Gain Drift, Offset Drift, Reference Drift and Total Bipolar Drift
are calculated in parts per million per oC as follows:
NOTE: FSR = Full Scale Output Voltage - Zero Scale Output
Voltage.
FSR = FSR (TH) - FSR (25oC),
or FSR (25oC) - FSR (TL).
VO = Steady State response to any input code.
Total Bipolar Drift (TBD) is the variation of output voltage
with temperature, in the bipolar mode of operation. It
represents the net effect of drift in Gain, Offset, Linearity and
Reference Voltage. Total Bipolar Drift values are calculated,
based on measurements as explained above. Gain and
Offset need not be calibrated to zero at 25oC. The specied
limits for TBD apply for any input code and for any power
supply setting within the specied operating range.
Accuracy
Linearity Error (Short for “Integral Linearity Error.” Also,
sometimes called “Integral Nonlinearity” and “Nonlinearity”.)
The maximum deviation of the actual transfer characteristic
from an ideal straight line. The ideal line is positioned
according to end-point linearity for D/A converter products
from Intersil Corporation, i.e., the line is drawn between the
end-points of the actual transfer characteristic (codes 00...0
and 11...1).
Differential Linearity Error The difference between one
LSB and the output voltage change corresponding to any
two consecutive codes. A Differential Nonlinearity of
±1 LSB
or less guarantees monotonicity.
Monotonicity The property of a D/A converter’s transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or
decreasing) input codes. That is, the only output response to
a code change is to remain constant, increase for Increasing
code, or decrease for decreasing code.
Total Error The net output error resulting from all internal
effects (primarily non-ideal Gain, Offset, Linearity and
Reference Voltage). Supply voltages may be set to any
values within the specied operating range. Gain and offset
errors must be calibrated to zero at 25oC. Then the specied
limits for Total Error apply for any input code and for any
temperature within the specied operating range.
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in
-VS,or+VS supplies. It is specied under DC conditions and
expressed as full scale range percent of change divided by
power supply percent change.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half-scale, i.e., the
major carry code transition from 011...1 to 100...0 or vice
versa. For example, if turn ON is greater than OFF for
011...1 to 100...0, an intermediate state of 000...0 exists,
such that, the output momentarily glitches toward zero
TABLE 1.
DIGITAL
INPUT
ANALOG OUTPUT
COMPLE-
MENTARY
STRAIGHT
BINARY
COMPLE-
MENTARY
OFFSET
BINARY
COMPLE-
MENTARY
TWO’S
COMPLEMENT
MSB...LSB
000...000
+ Full Scale
-LSB
100...000
Mid Scale-1 LSB
-1 LSB
+ Full Scale
111...111
Zero
- Full Scale
Zero
011...111
+1/2 Full Scale
Zero
- Full Scale
Invert MSB with external inverter to obtain CTC Coding.
GainDrift
FSR °C
FSR
--------------------------------
10
6
×
=
OffsetDrift
Offset °C
FSR
-------------------------------------
10
6
×
=
ReferenceDrift
V
REF
°C
()
V
REF
---------------------------------------
106
×
=
TotalBipolarDrift
V
O
°C
()
FSR
--------------------------------
10
6
×
=
PSS
FullScaleRange 100
×
FSR Nominal
()
-------------------------------------------------------------------
V
S
100
×
V
S(Nominal)
----------------------------------
-------------------------------------------------------------------
=
HI-DAC80V
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