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參數(shù)資料
| 型號： | HFA3861 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum (DSSS) baseband processor(直接序列擴頻基帶處理器) |
| 中文描述： | 直接序列擴頻（DSSS）基帶處理器（直接序列擴頻基帶處理器） |
| 文件頁數(shù)： | 13/35頁 |
| 文件大?。?/td> | 218K |
| 代理商： | HFA3861 |
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an extra 180 degree (
π
) rotation in addition to the standard
DQPSK modulation as shown in the table. The symbols of
the MPDU shall be numbered starting with “0” for the first
symbol for the purposes of determining odd and even
symbols. That is, the MPDU starts on an even numbered
symbol. The last data dibits d2, and d3 CCK encode the
basic symbol as specified in Table 6. This table is derived
from the formula above by setting
2 = (d2*pi)+ pi/2,
3 = 0,
and
4 = d3*pi. In the table d2 and d3 are in the order shown
and the complex chips are shown LSB to MSB (left to right)
with LSB transmitted first.
At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted
per symbol.
The first dibit (d0, d1) encodes
1 based on DQPSK. The
DQPSK encoder is specified in Table 6 above. The phase
change for
1 is relative to the phase
1 of the preceding
symbol. In the case of rate change, the phase change for
1
is relative to the phase
1 of the preceding CCK symbol. All
odd numbered symbols of the MPDU are given an extra 180
degree (
π
) rotation in accordance with the DQPSK
modulation as shown in Table 7. Symbol numbering starts
with “0” for the first symbol of the MPDU.
The data dibits: (d2, d3), (d4, d5), (d6, d7) encode
2,
3,
and
4 respectively based on QPSK as specified in Table 7.
Note that this table is binary, not Grey, coded.
TX Power Control
The transmitter power can be controlled by the MAC via two
registers. The first register, CR58, contains the results of
power measurements digitized by the HFA3861. By
comparing this measurement to what the MAC needs for
transmit power, the MAC can determine whether to raise or
lower the transmit power. It does this by writing the power
level desired to register CR31.
Clear Channel Assessment (CCA) and
Energy Detect (ED) Description
The clear channel assessment (CCA) circuit implements the
carriersenseportionofacarriersensemultipleaccess(CSMA)
networking scheme. The Clear Channel Assessment (CCA)
monitors the environment to determine when it is feasible to
transmit. The CCA circuit in the HFA3861 can be programmed
to be a function of RSSI (energy detected on the channel),
CS1, CS2, or both. The CCA output can be ignored, allowing
transmissions independent of any channel conditions. The
CCA in combination with the visibility of the various internal
parameters (i.e., Energy Detection measurement results), can
assist an external processor in executing algorithms that can
adapt to the environment. These algorithms can increase
network throughput by minimizing collisions and reducing
transmissions liable to errors.
There are three measures that can be used in the CCA
assessment. The receive signal strength indication (RSSI)
which indicates the energy at the antenna, CS1 and carrier
sense (CS2). CS2 becomes active only when a spread
signal with the proper PN code has been detected, and the
peak correlation amplitude exceeds a set threshold, so it
may not be adequate in itself.
CS1 becomes active anytime the AGC portion of the circuit
becomes unlocked, which is likely at the onset of a signal
that is strong enough to support 11Mbps, but may not occur
with the onset of a signal that is only strong enough to
support 1 or 2MBps. CS1 stays active until the AGC locks
and a CS2 assessment is done, if CS2 is false, then CS1 is
cleared, which deasserts CCA. If CS2 is true, then tracking
is begun, and CCA continues to show the channel busy. CS1
may occur at any time during acquisition as the AGC state
machine runs asynchronously with respect to slot times.
A CS2 evaluation occurs whenever the AGC has remained
locked for the entire data ingest period, when this happens,
CS2 is updated between 8 and 9
μ
s into the 10
μ
s dwell. If
CS1 is not active, two consecutive CS2’s are required to
advance the part to tracking.
The state of CCA is not guaranteed from the time RX_PE
goes high until the first CCA assessment is made. At the end
of a packet, after RXPE has been deasserted, the state of
CCA is also not guaranteed.
TABLE 5. DQPSK ENCODING TABLE
DIBIT PATTERN (d(0), d(1))
d(0) IS FIRST IN TIME
EVEN SYMBOLS
PHASECHANGE
(+j
ω)
ODD SYMBOLS
PHASECHANGE
(+j
ω
)
π
3
π
/2 (-
π
/2)
00
0
01
π
/2
π
11
0
10
3
π
/2 (-
π
/2)
π
/2
TABLE 6. 5.5Mbps CCK ENCODING TABLE
d2, d3
00 :
1j
1
1j
-1
1j
1
-1j
1
01 :
-1j
-1
-1j
1
1j
1
-1j
1
10 :
-1j
1
-1j
-1
-1j
1
1j
1
11 :
1j
-1
1j
1
-1j
1
1j
1
TABLE 7. QPSK ENCODING TABLE
DIBIT PATTERN (d(i), d(i+1))
d(i) IS FIRST IN TIME
PHASE
00
0
01
π
/2
π
10
11
3
π
/2 (-
π
/2)
HFA3861
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HFA3861IV | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925 | 2.4GHz - 2.5GHz 250mW Power Amplifier(2.4GHz - 2.5GHz 250mW 功率放大器) |
| HFA3926 | 2.0GHz - 2.7GHz 250mW Power Amplifier(2.0GHz - 2.7GHz 250mW 功率放大器) |
| HFA3926IA | 2.0GHz - 2.7GHz 250mW Power Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3861A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861AIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861AIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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