參數(shù)資料
型號(hào)： HFA3861
廠商： Intersil Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum (DSSS) baseband processor(直接序列擴(kuò)頻基帶處理器)
中文描述： 直接序列擴(kuò)頻（DSSS）基帶處理器（直接序列擴(kuò)頻基帶處理器）
文件頁(yè)數(shù)： 12/35頁(yè)
文件大?。?/td> 218K
代理商： HFA3861
12
Scrambler and Data Encoder Description
The modulator has a data scrambler that implements the
scrambling algorithm specified in the IEEE 802.11 standard.
This scrambler is used for the preamble, header, and data in
all modes. The data scrambler is a self synchronizing circuit.
It consist of a 7-bit shift register with feedback from specified
taps of the register. Both transmitter and receiver use the
same scrambling algorithm. The scrambler can be disabled
by setting CR32 bit 2 to 1.
NOTE: Be advised that the IEEE 802.11 compliant scrambler in the
HFA3861 has the property that it can lock up (stop scrambling) on
random data followed by repetitive bit patterns. The probability of this
happening is 1/128. The patterns that have been identified are all ze-
ros, all ones, repeated 10s, repeated 1100s, and repeated 111000s.
Any break in the repetitive pattern will restart the scrambler. To insure
that this does not cause any problem, the CCK waveform uses a ping
pongdifferentialcodingschemethatbreaksuprepetitive0spatterns.
Scrambling is done by a division using a prescribed
polynomial as shown in Figure 9. A shift register holds the
last quotient and the output is the exclusive-or of the data
and the sum of taps in the shift register. The taps are
programmable. The transmit scrambler seed is Hex 6C for
the long preamble or 1B for the short preamble and can be
set with CR36 or CR37.
For the 1Mbps DBPSK data rates and for the header in all
rates, the data coder implements the desired DBPSK coding
by differential encoding the serial data from the scrambler
and driving both the I and Q output channels together. For
the 2Mbps DQPSK data rate, the data coder implements the
desired coding as shown in the DQPSK Data Encoder table.
This coding scheme results from differential coding of dibits
(2 bits). Vector rotation is counterclockwise although bits 6
and 7 of configuration register
CR 1
can be used to reverse
the rotation sense of the TX or RX signal if desired.
Spread Spectrum Modulator Description
The modulator is designed to generate DBPSK, DQPSK, and
CCK spread spectrum signals. The modulator is capable of
automatically switching its rate where the preamble is
DBPSK modulated, and the data and/or header are
modulated differently. The modulator can support date rates
of 1, 2, 5.5 and 11Mbps. The programming details to set up
the modulator are given at the introductory paragraph of this
section. The HFA3861 utilizes Quadraphase (I/Q)
modulation at baseband for all modulation modes.
In the 1Mbps DBPSK mode, the I and Q Channels are
connected together and driven with the output of the
scrambler and differential encoder. The I and Q Channels
are then both multiplied with the 11-bit Barker word at the
spread rate. The I and Q signals go to the Quadrature
upconverter (HFA3724) to be modulated onto a carrier.
Thus, the spreading and data modulation are BPSK
modulated onto the carrier.
For the 2Mbps DQPSK mode, the serial data is formed into
dibits or bit pairs in the differential encoder as detailed
above. One of the bits from the differential encoder goes to
the I Channel and the other to the Q Channel. The I and Q
Channels are then both multiplied with the 11-bit Barker
word at the spread rate. This forms QPSK modulation at the
symbol rate with BPSK modulation at the spread rate.
CCK Modulation
The spreading code length is 8 and based on
complementary codes. The chipping rate is 11Mchip/s and
the symbol duration is exactly 8 complex chips long. The
following formula is used to derive the CCK code words that
are used for spreading both 5.5 and 11Mbps:
(LSB to MSB), where c is the code word.
The terms:
1,
2,
3, and
4 are defined below for
5.5Mbps and 11Mbps.
This formula creates 8 complex chips (LSB to MSB) that are
transmitted LSB first. The coding is a form of the generalized
Hadamard transform encoding where
1 is added to all code
chips,
2 is added to all odd code chips,
3 is added to all
odd pairs of code chips and
4 is added to all odd quads of
code chips.
The phases
1 modify the phase of all code chips of the
sequence and are DQPSK encoded for 5.5 and 11Mbps.
This will take the form of rotating the whole symbol by the
appropriate amount relative to the phase of the preceding
symbol. Note that the last chip of the symbol defined above
is the chip that indicates the symbol’s phase.
For the 5.5Mbps CCK mode, the output of the scrambler is
partitioned into nibbles. The first two bits are encoded as
differential modulation in accordance with Table 5 . All odd
numbered symbols of the short Header or MPDU are given
TABLE 4. DQPSK DATA ENCODER
PHASE SHIFT
DIBIT PATTERN (d0, d1)
d0 IS FIRST IN TIME
0
00
+90
01
+180
11
-90
10
FIGURE 9. SCRAMBLING PROCESS
Z
-1
Z
-2
Z
-3
Z
-4
Z
-5
Z
-6
Z
-7
XOR
SERIAL DATA
IN
XOR
SERIAL
DATA OUT
c
e
j
1
2
3
4
+
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+
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(
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+
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=
HFA3861
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