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參數(shù)資料
| 型號(hào)： | HFA3860B |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器) |
| 中文描述： | 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)頻基帶處理器） |
| 文件頁數(shù)： | 35/40頁 |
| 文件大小： | 330K |
| 代理商： | HFA3860B |
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2-35
Bits 7:0
Test Bus Address = 1Eh to 1Fh
Reserved
Test 7:0 + TestCLK = 0
CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS (Continued)
Supplies address for test pin outputs and Test Bus Monitor Register
CONFIGURATION REGISTER 29 ADDRESS (74h) TEST BUS MONITOR
Bits 7:0
Maps test bus pins 7:0 to read only value 7:0 when test bus address is supplied by CR 28
CONFIGURATION REGISTER 30 ADDRESS (78h) TEST REGISTER 1
Bits 7
PN Generator for Fault Test
0 = Normal
1 = Enabled
Bit 6
High rate Jump Clock Control
0 = Enable HR Jmpclk
1 = Disable HR Jmpclk
Bit 5
HR Demod XOR to Test Bus Enable
0 = Normal
1 = Enabled
Bit 4
Random Address to Test Bus
0 = Normal
1 = Enabled
Bit 3
Faster Cal
0 = Normal
1 = Enabled
When enabled, the 1kHz clock used to update the A/D cal bits is increased to 22kHz.
Bit 2
A/D Cal Test Mode
0 = Normal
1 = Enabled
When enabled, the 5 A/D cal bits come from CR3<4:0> to allow direct control.
Bit 1
A/D Test Mode
0 = Normal
1 = Enabled
When enabled, this bit causes all 12 bits of A/D outputs (6 RSSI, 3 I, 3 Q) to be directly output on pins of the HFA3860B.
Modem is nonfunctional.
Bit 0
Loop Back
0 = Normal
1 = Enabled
When enabled, this bit routes the I and Q outputs to the I and Q inputs of the modem. The 3-bit I&Q A/Ds are bypassed.
CONFIGURATION REGISTER 31 ADDRESS (7Ch) RX CONTROL
Bits 7:5
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 4
Waveform modulation selection for 5.5 and 11Mbps
0 = BMBOK/QMBOK (Binary M-ary Bi-orthogonal Keying or Quaternary M-ary Bi-orthogonal Keying)
1 = CCK (Complementary Code Keying)
Bit 3
Type of differential encoding/decoding scheme for 5.5 and 11Mbps CCK modulation
0 = Standard differential encoding/decoding
1 = Differential encoding/decoding with odd symbols given an extra 180 degree rotation (IEEE 802.11 compliant)
Bit 2
RX QPSK Acquire
0 = Normal, will not acquire on QPSK, only on BPSK
1 = Acquire on QPSK (2MBPS) see Tech Brief 365.
Bit 1
Disable Control
0 = ED disabled after MD_RDY active
1 = ED runs continuously
Bit 0
CCA Type Select
1 = RAW CCA, updates every ANT Dwell
0 = Enhanced CCA
HFA3860B
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PDF描述 |
|---|---|
| HFA3860 | 3.3V 288-mc CPLD |
| HFA3860IV | 11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| HFA3860IV96 | 11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861A | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器) |
| HFA3861B | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3860BIV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860BIV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860IV WAF | 制造商:Harris Corporation 功能描述: |
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