參數(shù)資料
型號: HFA3724IN
廠商: HARRIS SEMICONDUCTOR
元件分類: 衰減器
英文描述: 400MHz Quadrature IF Modulator/Demodulator
中文描述: MODEM
文件頁數(shù): 18/24頁
文件大?。?/td> 186K
代理商: HFA3724IN
18
Quadrature Up Converter
The Quadrature up converter mixers are also based on a
doubly balanced Gilbert Cell design. “I” and “Q” Up converter
signalsaresummedandbufferedtogetherthroughasingleend
open collector stage. As with the demodulators, both modulator
mixers are driven from the same quadrature LO generator. It
featuresa
±
4
o
and0.5dBofphaseandamplitudebalanceupto
400MHz which are reflected into its SSB characteristics. For “I”
and “Q” differential inputs of 500mV
P-P
, 90
o
apart, the carrier
feedthrough or LO leakage is typical -30dBc into 250
with a
sideband suppression of minimum 26dBc at 400MHz. Carrier
feedthrough can be further improved by disabling the LO output
port (please refer to pin#50 description) or using a DC bias
network as in Figure 25. Featuring an output compression level
of 1V
P-P
, the modulator output can generate a CW signal of
typical -10dbm into 250
(158mV
RMS
) when differential DC
inputs of 500mV
P-P
(equivalent to applying
±
125mV ground
referenced levels from the DC bias quiescent point of the
device input) are applied to both “I” and “Q” inputs. Four
quadrant phase shifts of the carrier output, like in Vector
Modulator applications, can be set by proper choice of “I” and
“Q” DC differential inputs, such that the square root of the sum
of the squares of I and Q is constant.
Although specified to drive a 250
load, the HFA3724
modulator open collector output enables user designed
output matching networks to suit any application interface.
The nominal AC current capability of this port is of
1.3mA
RMS
, which is shared between the termination resistor
and the load for I and Q differential DC inputs of 500mV
P-P
as explained above. (Use 70.7% of this AC capability for I
and Q quadrature signals in case of SSB generation).
Programmable Low Pass Filters
These filters are implemented using a 5th order Butterworth
architecture. They are multiplexed, i.e., the same filter bank
is used for both transmit and receive modes.
The filter block, in the transmit mode is set to accept digital
(TTL threshold) input data for “I” and “Q” signals and is
programmable with 4 frequency cutoffs: (2.2MHz, 4.4MHz,
8.8MHz and 17.8MHz). Digital control pins are used to
switch all programmed cutoff modes. The user can design a
multi data rate transceiver or simply hardwire these inputs.
An external resistor is used to fine tune the cut off
frequencies for each setting within
±
20% of the nominal
value. This feature is often needed to fulfill requirements of
spectral mask compliance at the antenna output.
The “I” and “Q” filter matching is within 2
o
for phase and
0.25dB for amplitude at the passband. Group delay
characteristics follow closely a theoretical 5th order
Butterworth design.
When in the receive mode, the filters exhibit a 0dB of gain
with differential inputs and single ended outputs.
In the transmit mode, the digital ground referenced “I” and
“Q” input signals are level shifted, shaped and buffered with
constant driving differential outputs of 550mV
P-P
.
Baseband Digital Interfacing
Special precautions must be taken when interfacing the
HFA3724 to a digital baseband processor: Large TTL signal
swings, overshoots and current spikes, must be carefully
considered when dealing with the generation of analog
spread spectrum signals which are relatively much smaller in
energy per bandwidth.
In order to avoid distortion or spurious tones on the analog
transmit path, it may be necessary to decrease and/or limit
digital excursions as much as possible without
compromising the specifications. Figure 26 shows a
simplified block diagram of the Transmit digital inputs.
1K
1K
1K
1K
43K
50K
43K
50K
M
M
M
M
40
39
38
37
FIGURE 25. CARRIER NULL BIASING
HFA3724
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