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參數(shù)資料
| 型號： | HDMP-1546A |
| 英文描述： | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| 中文描述： | 光纖通道收發(fā)器芯片（光纖通道收發(fā)器芯片） |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 246K |
| 代理商： | HDMP-1546A |
9
Output Jitter Characteristics
T
A
= 0
°
to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
RJ
[1]
Random Jitter at DOUT, the High Speed Electrical Data Port, specified as
1 sigma deviation of the 50% crossing point (RMS)
DJ
[1]
Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk)
Parameter
Units
ps
Typ.
8
ps
15
Note:
1. Defined by Fibre Channel Specification Rev 4.1, Annex A, Section A.4 and tested using measurement method shown in Figure 8.
Thermal and Power Temperature Characteristics,
T
A[1]
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
P
D,TRx[2,3]
Transceiver Power Dissipation, Outputs Open, Parallel Data
has 5 Ones and 5 Zeroes
P
D,TRx[2,3,4]
Transceiver Power Dissipation, Outputs Connected per
Recommended Bias Terminations with Idle Pattern
Θ
jc[5]
Thermal Resistance, Junction to Case
Parameter
Units
mW
Typ.
630
Max.
850
mW
675
900
HDMP-1536A
HDMP-1546A
°
C/Watt
11
8
Notes:
1. Device tested and characterized under T
A
conditions specified, with T
C
monitored at approximately 20
°
higher than T
A
.
2. P
D
is obtained by multiplying the max V
CC
by the max I
CC
and subtracting the power dissipated outside the chip at the high speed
bias resistors.
3. Typical value specified with V
CC
= 3.3 volts, maximum value specified with V
CC
= 3.45 volts.
4. Specified with high speed outputs biased with 150
resistors and receiver TTL outputs driving 10 pF loads.
5. Based on independent package testing by Agilent Technologies.
Θ
ja
for these devices is 56
°
C/Watt for the HDMP-1536A and
51
°
C/Watt for the HDMP-1546A.
Θ
ja
is measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual
junction temperature in a given application, use the following: Tj = T
C
+ (
Θ
jc
x Pd), where T
C
is the case temperature measured
on the top center of the package and P
D
is the power being dissipated.
Figure 8. Transmitter Jitter Measurement Method.
a. Block Diagram of RJ Measurement Method.
b. Block Diagram of DJ Measurement Method.
70841B
PATTERN
GENERATOR*
83480A
OSCILLOSCOPE
HDMP-1536A
70311A
CLOCK SOURCE
+ DATA
- DATA
0000011111
TRIGGER
CH1
CH2
+DOUT
-DOUT
REFCLK LOOPEN
Tx[0..9]
BIAS
TEE
1.4 V
0011111000
(STATIC K28.7)
1.0625 GHz
106.25 MHz
* PATTERN
GENERATOR
PROVIDES A
DIVIDE BY
10 FUNCTION.
70841B
PATTERN
GENERATOR*
83480A
OSCILLOSCOPE
HDMP-1536A
70311A
CLOCK SOURCE
+ DATA
- DATA
+K28.5, -K28.5
TRIGGER
CH1
CH2
+DOUT
-DOUT
REFCLK
LOOPEN
Tx[0..9]
1.0625 GHz
106.25 MHz
ENBYTSYNC
Rx[0..9]
-DIN
+DIN
DIVIDE
BY 2
CIRCUIT
DIVIDE
BY 10
CIRCUIT
(DUAL
OUTPUT)
VARIABLE
DELAY
TTL
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| HDMP-1636A | Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器) |
相關(guān)代理商/技術(shù)參數(shù) |
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| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
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| HDMP-1637A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.25 GBd SerDes Circuit with Differential PECL Clock Inputs for Gigabit Ethernet Applications |
| HDMP-1638 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs |
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