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參數(shù)資料
| 型號： | HDMP-1546A |
| 英文描述： | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| 中文描述： | 光纖通道收發(fā)器芯片（光纖通道收發(fā)器芯片） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 246K |
| 代理商： | HDMP-1546A |
5
HDMP-1536/46A (Transmitter Section)
Timing Characteristics
T
A[1]
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
t
setup
t
hold
t_txlat
[2]
Parameter
Setup Time
Hold Time
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
2
1.5
Typ.
Max.
3.5
4.4
Notes:
1. Device tested and characterized under T
A
conditions specified, with T
C
monitored at approximately 20
°
higher than T
A
.
2. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
Figure 3. Transmitter Section Timing.
Figure 4. Transmitter Latency.
DATA
DATA
TX[0]-TX[9]
t
setup
t
hold
REFCLK
DATA
DATA
DATA
1.4 V
2.0 V
0.8 V
DATA BYTE B
DATA BYTE C
TX[0]-TX[9]
DATA BYTE A
± DOUT
1.4 V
DATA BYTE B
t_txlat
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
REFCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1536A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1636 | Software |
| HDMP-1646 | Gigabit Ethernet Transceiver Chip |
| HDMP-1646A | Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器) |
| HDMP-1636A | Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
| HDMP-1636A | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet and Fibre Channel SerDes ICs |
| HDMP-1636AG | 制造商:PMC-Sierra 功能描述:1.06/1.25 GB SerDes for GB EOL301107 |
| HDMP-1637A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.25 GBd SerDes Circuit with Differential PECL Clock Inputs for Gigabit Ethernet Applications |
| HDMP-1638 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs |
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