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參數(shù)資料
| 型號： | HDMP-1546 |
| 英文描述： | Fibre Channel Transceiver Chip |
| 中文描述： | 光纖通道收發(fā)器芯片 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 259K |
| 代理商： | HDMP-1546 |
701
HDMP-1536/46 (Receiver Section)
Timing Characteristics
T
A[1]
= 0
°
C to +60
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
b_sync
[2,3]
Bit Sync Time
t
valid_before
Time Data Valid Before Rising Edge of RBC
t
valid_after
Time Data Valid After Rising Edge of RBC
t
duty
RBC Duty Cycle
t
A-B[4]
Rising Edge Time Difference
t_rxlat
[5]
Receiver Latency
Parameter
Units
bits
nsec
nsec
%
nsec
nsec
bits
Min.
Typ.
Max.
2500
3
3.8
3.5
1.5
40
8.9
60
9.9
9.4
24.5
26
Notes:
1. Device tested and characterized under T
A
conditions specified, with T
C
monitored at approximately 20
°
higher than T
A
.
2. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
3. Tested using C
PLL
= 0.1
μ
F.
4. The RBC clock skew is calculated as t
A-B(max)
- t
A-B(min)
.
5. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (as
defined as the first edge of the first serial) and the clocking out of that parallel word (defined by the rising edge of the receive byte
clock, either RBC1 or RBC0).
Figure 6. Receiver Latency.
Figure 5. Receiver Section Timing.
DATA
DATA
RX[0]-RX[9]
t
valid_before
t
valid_after
RBC1
K28.5
DATA
DATA
1.4 V
2.0 V
0.8 V
2.0 V
BYTSYNC
RBC0
t
A-B
0.8 V
1.4 V
DATA BYTE A
DATA BYTE D
RX[0]-RX[9]
DATA BYTE D
± DIN
1.4 V
t_rxlat
R5
R6
R7
R8
R9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R2
R3
R4
R5
RBC1/0
DATA BYTE C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1546A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1536A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1636 | Software |
| HDMP-1646 | Gigabit Ethernet Transceiver Chip |
| HDMP-1646A | Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1546A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-TRANSCEIVER |
| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
| HDMP-1636A | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet and Fibre Channel SerDes ICs |
| HDMP-1636AG | 制造商:PMC-Sierra 功能描述:1.06/1.25 GB SerDes for GB EOL301107 |
| HDMP-1637A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.25 GBd SerDes Circuit with Differential PECL Clock Inputs for Gigabit Ethernet Applications |
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