- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370499 > HDMP-1546 Fibre Channel Transceiver Chip PDF資料下載
參數(shù)資料
| 型號： | HDMP-1546 |
| 英文描述： | Fibre Channel Transceiver Chip |
| 中文描述： | 光纖通道收發(fā)器芯片 |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 259K |
| 代理商： | HDMP-1546 |
709
Figure 12. Power Supply Bypass.
Start-up Procedure:
The transceiver start-up
procedure(s) use the following
conditions: V
CC
= +3.3 V
±
5%
and REFCLK = 106.25 MHz
±
100 ppm.
Auto-Lock Used Exclusively
Set -LCKREF = 1 and apply valid
data using a balanced code such
as 8B/10B. Frequency lock
occurs within 500
μ
s. After
frequency lock, phase lock occurs
within 2500 bit times.
User Controlled
Set -LCKREF = 0 for at least 500
μ
s (frequency lock will occur
within 500
μ
s). After valid
8B/10B data is applied to the Rx
input, set -LCKREF=1. Phase
lock will occur within 2500 bit
times. In this case, asserting
-LCKREF = 0 forces the Rx PLL
to fully phase and frequency lock
onto the reference clock
(REFCLK) disregarding the serial
data stream completely. Asserting
-LCKREF = 0 is an option for
users that want full control
during the frequency acquisition
process.
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
Bypass capacitors should be used
and placed as close as possible to
the appropriate power supply
pins of the HDMP-1536/46 as
shown on the schematic of Figure
12. All bypass chip capacitors are
0.1
μ
F. The V
CC
_RXA and
V
CC
_TXA pins are the analog
power supply pins for the PLL
sections. The voltage into these
pins should be clean with
minimum noise. The PLL loop
filter capacitors and their pin
locations are also shown on
Figure 12. Notice that only two
capacitors are required: C
PLLT
for
the transmitter and C
PLLR
for the
receiver. Nominal capacitance is
0.1
μ
F. The voltage across the
capacitors is on the order of 1
volt, so the capacitor can be a
low voltage type and physically
small. The PLL capacitors are
placed physically close to the
appropriate pins on the HDMP-
1536/46. Keeping the lines short
will prevent them from picking
up stray noise from surrounding
lines or components.
RXCAP0
V
CC
_RXTTL
V
CC
_RXTTL
G
TOP VIEW
GND_RXTTL
GND_TXTTL
V
CC
_TXTTL
V
CC
_TXTTL
GND_TXTTL
GND_TXA
TXCAP1
V
C
_
V
C
_
V
C
_
G
V
C
_
G
V
C
_
V
C
_
G
V
C
_
R
* SUPPLY VOLTAGE INTO V
_RXA AND V
_TXA SHOULD
BE FROM A LOW NOISE SOURCE. ALL BYPASS CAPACITORS
AND PLL FILTER CAPACITORS ARE 0.1 μF.
V
C
_
G
V
CC
V
CC
*
V
CC
GND_RXTTL
T
V
C
_
G
V
C
_
G
V
C
_
V
C
_
C
PLLT
V
CC
*
C
PLLR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1546A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1536A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1636 | Software |
| HDMP-1646 | Gigabit Ethernet Transceiver Chip |
| HDMP-1646A | Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1546A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-TRANSCEIVER |
| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
| HDMP-1636A | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet and Fibre Channel SerDes ICs |
| HDMP-1636AG | 制造商:PMC-Sierra 功能描述:1.06/1.25 GB SerDes for GB EOL301107 |
| HDMP-1637A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.25 GBd SerDes Circuit with Differential PECL Clock Inputs for Gigabit Ethernet Applications |
發(fā)布緊急采購，3分鐘左右您將得到回復。