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參數(shù)資料
| 型號： | HD74CDC857 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3/2.5-V Phase-lock Loop Clock Driver |
| 中文描述： | 3.3/2.5-V鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 54K |
| 代理商： | HD74CDC857 |
HD74CDC857
7
Pin Function
Pin name
No.
Type
Description
AGND
17
Ground Analog ground. AGND provides the ground reference for the
analog circuitry.
AV
CC
16
Power
Analog power supply. AV
provides the power reference for the
analog circuitry. In addition, AV
can be used to bypass the PLL
for test purposes. When AV
is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
CLK,
CLK
13, 14
I
Clock input. CLK provides the clock signal to be distributed by the
HD74CDC857 clock driver. CLK is used to provide the reference
signal to the integrated PLL that generates the clock output
signals. CLK must have a fixed frequency and fixed phase for the
PLL to obtain phase lock. Once the circuit is powered up and a
valid CLK signal is applied, a stabilization time is required for the
PLL to phase lock the feedback signal to its reference signal.
FBIN
, FBIN
35, 36
I
Feedback input. FBIN provides the feedback signal to the internal
PLL. FBIN must be hard-wired to FBOUT to complete the PLL.
The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
FBOUT,
FBOUT
32, 33
O
Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
G
37
I
Output bank enable. G is the output enable for all outputs. When
G is low, VCO will stop and all outputs are disabled to a high
impedance state. When G will be returned high, PLL will re-
synchroniz to CLK frequency and all outputs are enabled.
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
Ground Ground
V
DDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
Power
Power supply
Y
3, 5, 10, 20,
22, 27, 29,
39, 44, 46
O
Clock outputs. These outputs provide low-skew copies of CLK.
Y
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
O
Clock outputs. These outputs provide low-skew copies of
CLK
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD74CDCF2509B | 3.3-V Phase-lock Loop Clock Driver(3.3V鎖相環(huán)時鐘驅(qū)動器) |
| HD74CDCF2510B | 3.3-V Phase-lock Loop Clock Driver(3.3V鎖相環(huán)時鐘驅(qū)動器) |
| HD74CDCV857 | 2.5-V Phase-lock Loop Clock Driver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HD74CDCF2509BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDCF2510BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDCF2510BTEL-E | 制造商:Renesas Electronics Corporation 功能描述:PLL CLOCK DRIVERS - Tape and Reel |
| HD74CDCV857RTE | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDCV857RTE-E | 制造商:Renesas Electronics Corporation 功能描述:CLOCK GENERATOR - Tape and Reel |
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