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參數(shù)資料
| 型號(hào)： | HD74CDC857 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3/2.5-V Phase-lock Loop Clock Driver |
| 中文描述： | 3.3/2.5-V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 54K |
| 代理商： | HD74CDC857 |
HD74CDC857
4
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit Conditions
Supply voltage
AV
CC
(1)
AV
CC
(2)
V
DDQ
2.3
—
2.7
V
f
CLK
= 100 to 150 MHz
f
CLK
= 130 to 150 MHz
3.0
—
3.6
Output supply voltage
2.3
—
2.7
V
DC input signal voltage
*1
–0.3
—
V
DDQ
+0.3
—
V
All pins
High level input voltage
V
IHD
V
ILD
V
IHG
V
ILG
V
ID
1.7
—
V
Low level input voltage
—
—
0.8
V
High level input voltage
1.7
—
V
DDQ
+0.3
0.7
V
G input pin
Low level input voltage
–0.3
—
V
G input pin
Differential input signal voltage
*2
0.36
—
V
DDQ
+0.6
V
DDQ
+0.6
0.5
×
V
DDQ
+0.35
V
DC
0.7
—
AC
Differential cross point voltage
*3
0.5
×
V
DDQ
–0.35
—
V
Reference voltage
*4
V
ref
I
OH
I
OL
SR
1.15
1.25
1.35
V
Vref = 0.5
×
V
DDQ
Output current
–7
—
–30
mA
7
—
30
Input slew rate
1
—
—
V/ns
Operating temperature
Notes:
T
a
0
—
70
°
C
Unused inputs must be held high or low to prevent them from floating.
Feedback inputs (FBIN,
FBIN
) may float when the device is in low power mode.
1. DC input signal voltage specifies the allowable dc execution of differential input.
2. Differential input signal voltage specifies the differential voltage |VTR–VCP| required for
switching, where VTR is the true input level and VCP is the complementary input level.
3. Differential cross point voltage is expected to track variations of V
DDQ
and is the voltage at which
the differential signals must be crossing. (See figure1-1)
4. V
is the reference DC level, when using single clock input. When CLK (pin#13) is single ended
input,
CLK
(pin#14) must be set V
ref
. (See figure1-2)
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