
Table 1-1   Features 
Feature
CPU
Description
General-register machine
  Eight 16-bit general registers
  Five 8-bit and two 16-bit control registers
High speed
  Maximum clock rate: 10 MHz (oscillator frequency:  20 MHz, R-mask versions)
16 MHz (oscillator frequency:  32 MHz, S-mask versions)
Expanded operating modes supporting external memory
  Minimum mode:  up to 64-kbyte address space
  Maximum mode:  up to 1 M-byte address space
Highly orthogonal instruction set
  Addressing modes and data size can be specified independently for 
each instruction
1.5 Addressing modes
  Register-register operations
  Register-memory operations
Instruction set optimized for C language
  Special short formats for frequently-used instructions and addressing modes
  2-kbyte high-speed RAM on-chip
  32-kbyte programmable or masked ROM on-chip
  2-kbyte high-speed RAM on-chip
  62-kbyte programmable or masked ROM on-chip
Each channel provides:
  1 free-running counter (which can count external events)
  2 output-compare registers
  1 input capture register
  One 8-bit up-counter (which can count external events)
  2 time constant registers
  Generates pulses with any duty ratio from 0 to 100%
  Resolution:  1/250
  An overflow generates a nonmaskable interrupt
  Can also be used as an interval timer
Memory
(H8/534)
Memory
(H8/536)
16-Bit free-
running 
timer (FRT)
(3 channels)
8-Bit timer
(1 channel)
PWM timer 
(3 channels)
Watchdog 
timer (WDT)
(1 channel)
2