
Table 9-1   Input/Output Port Summary
Expanded Modes
Single-Chip Mode
(Mode 7)
Port
Port 1 8-Bit input/output P1
7
 / TMO
Description
Pins
Mode 1 Mode 2 Mode 3 Mode 4
These input/output pins double as IRQ
1
, 
P1
6
 / IRQ
1
 / IRQ
0
, and ADTRG inputs, and as an 
ADTRG
output pin (TMO) for the 8-bit timer.
P1
5
 / IRQ
0
P1
4
 / WAIT These pins function as WAIT, BREQ,
P1
3
 / BREQ and BACK when necessary control-
P1
2
 / BACK register bits are set to 1.
P1
1
 / E
These pins function as input pins or as 
P1
0
 / 
clock (E, ) output pins, depending on 
the data direction register setting.
Port 2 5-Bit input/output P2
4
 / WR
Bus control signal outputs
port
P2
3
 / RD
(WR, RD, DS, R/W, AS)
P2
2
 / DS
P2
1
 / R/W
P2
0
 / AS
Port 3 8-Bit input/output P3
7
 - P3
0
 / 
Data bus (D
7
 – D
0
)
port
D
7
 – D
0
Port 4 8-Bit input/output P4
7
 – P4
0
 / Low address bus (A
7
 – A
0
)
port
A
7
 – A
0
Can drive a LED
Port 5 8-Bit input/output P5
7
 – P5
0
 / High
port
A
15
 – A
8
address address address address
Built-in input 
bus
pull-up (MOS)
(A
15
 –
A
8
)
Port 6 4-Bit input/output P6
3
 / PW
3
 /
Output for PWM
port
IRQ
5
 / A
19
timers 1, 2, and
Built-in input 
P6
2
 / PW
2
 /
3, input for IRQ
2
pull-up (MOS)
IRQ
4
 / A
18
to IRQ
5
, and 
P6
1
 / PW
1
 /
input/output port.
IRQ
3
 / A
17
P6
0
 / IRQ
2
 /
A
16
Input/output
port
Input/output
port
Input/output
port
Input/output
port
High 
High
High
Input/output
port
bus if
DDR is
set to 1
bus
(A
15
 –
A
8
)
Page
address address
bus
(A
19
 –
A
16
)
bus if
DDR is
set to 1
Page  
Input/output
port
bus if DDR
is set to 1,
input port 
and IRQ
2
to IRQ
5
input pins if
DDR is set
to 0
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