參數(shù)資料
型號(hào): HD-6409883
廠商: Intersil Corporation
英文描述: CMOS Manchester Encoder-Decoder
中文描述: 的CMOS曼徹斯特編碼,解碼器
文件頁數(shù): 5/7頁
文件大?。?/td> 135K
代理商: HD-6409883
139
Output Fall Time (All except CO)
tf
From 3.5 to 1.0V
CL = 50pF
1, 2
-55
o
C
T
A
+125
o
C
-
50
ns
CO Rise Time
tr
From 1.0 to 3.5V
CL = 20pF
1, 2
-55
o
C
T
A
+125
o
C
-
11
ns
CO Fall Time
tf
From 3.5 to 1.0V
CL = 20pF
1, 2
-55
o
C
T
A
+125
o
C
-
11
ns
ECLK to BZO, BOO
tCE3
1, 3
-55
o
C
T
A
+125
o
C
0.5
1.0
DBP
CTS Low to BZO BOO Enabled
tCE4
1, 3
-55
o
C
T
A
+125
o
C
0.5
1.5
DBP
CTS Low to ECLK Enabled
tCE5
1, 3
-55
o
C
T
A
+125
o
C
10.5
11.5
DBP
CTS High to ECLK Disabled
tCE6
1, 3
-55
o
C
T
A
+125
o
C
-
1.0
DBP
CTS High to BZO BOO Disabled
tCE7
1, 3
-55
o
C
T
A
+125
o
C
1.5
2.5
DBP
UDI to SDO, NVM
tCD1
1, 3
-55
o
C
T
A
+125
o
C
2.5
3.0
DBP
RST Low to DCLK, SDO, NVM Low
tCD3
1.3
-55
o
C
T
A
+125
o
C
0.5
1.5
DBP
RST High to DCLK, Enabled
tCD4
1, 3
-55
o
C
T
A
+125
o
C
0.5
1.5
DBP
UDI to BZO, BOO
tR1
1, 3
-55
o
C
T
A
+125
o
C
0.5
1.0
DBP
UDI to SDO, NVM
tR3
1, 3
-55
o
C
T
A
+125
o
C
2.5
3.0
DBP
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested.
2. Guaranteed via characterization at initial device design and after major process and/or design changes.
3. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X,
one DBP = 32 Clock Cycles.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
Group A
-
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D
Samples/5005
1, 7, 9
TABLE 3. HD-6409/883 ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
HD-6409/883
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