參數(shù)資料
型號(hào)： HD-6409883
廠商： Intersil Corporation
英文描述： CMOS Manchester Encoder-Decoder
中文描述： 的CMOS曼徹斯特編碼，解碼器
文件頁數(shù)： 3/7頁
文件大?。?/td> 135K
代理商： HD-6409883
137
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage Applied. . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Temperature Range. . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . .50ns Max
Sync. Transition Span (t2) . . . . . . . . . 1.5 DBP Typical, (Notes 1, 2)
Short Data Transition Span (t4) . . . . . 0.5 DBP Typical, (Notes 1, 2)
Long Data Transition Span (t5) . . . . . 1.0 DBP Typical, (Notes 1, 2)
Zero Crossing Tolerance (tCD5) . . . . . . . . . . . . . . . . . . . . . (Note 3)
Thermal Resistance
CERDIP Package . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
Storage Temperature Range . . . . . . . . . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300
o
C
θ
JA
(
o
C/W)
83
95
θ
JC
(
o
C/W)
23
26
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. DBP - Data Bit Period.
Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X; one DBP = 32 Clock Cycles.
2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by
±
2 IX clock cycles (16X mode)
or
±
6 IX clock cycles (32X mode).
3. The maximum zero crossing tolerance is
±
2 IX clock cycles (16X mode) or
±
6 IX clock cycles (32X mode) from the nominal.
TABLE 1. HD-6409/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Logic “1” Input Voltage
VIH
VCC = 4.5V
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
70%
VCC
-
V
Logic “0” Input voltage
VIL
VCC = 4.5V
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-
20% VCC
V
Logic “1” Input Voltage
(RST)
VIHR
VCC = 5.5V
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
VCC -0.5
-
V
Logic “0” Input Voltage
(RST)
VILR
VCC = 4.5V
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-
GND +0.5
V
Logic “1” Input Voltage (IX)
VIHC
VCC = 5.5V
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
VCC -0.5
-
V
Logic “0” Input Voltage (IX)
VlLC
VCC = 4.5V
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-
GND +0.5
V
Input Leakage Current
(Except IX)
II
VIN = VCC or
GND
VCC = 5.5V
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-1.0
+1.0
μ
A
Input Leakage Current
(IX)
II
VlN = VCC or
GND
VCC
=
5.5V
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-20
+20
μ
A
I/O Leakage Current
IO
VOUT = VCC
or GND
VCC = 5.5V
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-10
+10
μ
A
Output HIGH Voltage
(All except OX)
VOH
IOH = -2.0mA
VCC = 4.5V
(Note 1)
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
VCC -0.4
-
V
Output LOW Voltage
(All except OX)
VOL
IOL = +2.0mA
VCC = 4.5V
(Note 1)
1, 2, 3
-55
o
C
≤
T
A
≤
+125
o
C
-
0.4
V
HD-6409/883
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