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參數(shù)資料
| 型號(hào)： | HC4053 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | IC-VLTG REG 125V-1A |
| 中文描述： | 模擬多路復(fù)用器/解復(fù)用器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 87K |
| 代理商： | HC4053 |
SL74HC4053
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, Channel-Select to
Analog Output (Figures 8 and 9)
2.0
4.5
6.0
370
74
63
465
93
79
550
110
94
ns
t
PLH
, t
PHL
Maximum Propagation Delay , Analog Input to
Analog Output (Figures 10 and 11)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay , Enable to Analog
Output (Figures 12 and 13)
2.0
4.5
6.0
290
58
49
364
73
62
430
86
73
ns
t
PZL
, t
PZH
Maximum Propagation Delay , Enable to Analog
Output (Figures 12 and 13)
2.0
4.5
6.0
345
69
59
435
87
74
515
103
87
ns
C
IN
Maximum Input Capacitance, Channel-Select or
Enable Inputs
-
10
10
10
pF
C
I/O
Maximum Capacitance
Analog I/O
All Switches Off
-
35
35
35
pF
Common O/I
-
50
50
50
Feedthrough
-
1.0
1.0
1.0
Power Dissipation Capacitance (Per Package)
(Figure 15)
Typical @25
°
C,V
CC
=5.0 V, V
EE
=0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
45
pF
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