參數(shù)資料
型號(hào)： HB7121
廠商： Hynix Semiconductor Inc.
英文描述： CMOS IMAGE SENSOR With 8-bit ADC
中文描述： CMOS圖像傳感器的8位ADC
文件頁(yè)數(shù)： 11/29頁(yè)
文件大?。?/td> 391K
代理商： HB7121
HB7121B
Semiconductor Inc.
System IC SBU
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume
any responsibility for use of circuits described. NO patent licenses are implied.
DA21000601R_1.0 - 11 - 2001 Hnix System IC SBU
n
Mode B [5:4] :
data_type
(data types) <
default value : 00b>
These bits define output pixel data types. For Correlated Double Sampling(CDS), every the
pixel of image sensor are measured twice, reference and data respectively, and reference
values or data values can be read out through pixel data pins selectively using these control
bits. To remove the noise caused by circuit, i.e.
Fixed Pattern
Noise, the image sensor
performs the CDS in default value. Three output data types are supported as follows.
Bit
Output data type
00
Data level - Reference level
01
Reference level
10
Data level
11
Reserved
n
Mode B[3] :
hs_out
(HSYNC output configuration) <
default value : 0b>
This bit offers two types output style about HSYNC signal. HSYNC only mode and HSYNC &
internal clock mode. If the
hs_out
is set to one, HSYNC output signal is ANDed signal of
internal pixel clock and data valid. Otherwise HSYNC output pin keep data high state during
valid output period. When HSYNC & internal clock mode is set, HSYNC output can be used
as a pixel data output clock.
data valid
MUX HSYNC
pixel clock
Mode B[3]
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