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參數(shù)資料
| 型號(hào)： | HB54R1G9F2-A75B |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 1GB Registered DDR SDRAM DIMM |
| 中文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DUAL LEAD OUT, SOCKET TYPE, DIMM-184 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大小： | 146K |
| 代理商： | HB54R1G9F2-A75B |
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HB54R1G9F2-A75B/B75B/10B
Data Sheet E0089H40 (Ver. 4.0)
13
Pin Capacitance (TA = 25°C, VCC, VCCQ = 2.5V ± 0.2V)
Parameter
Symbol
Pins
max.
Unit
Notes
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/S, CKE
CK, /CK
10
pF
1, 3
Input capacitance
Data and DQS input/output
capacitance
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2,
VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
CI2
20
pF
1, 3
CO
DQ, DQS, CB, DM
20
pF
1, 2, 3
Timing Parameter Measured in Clock Cycle for Registered DIMM
Number of clock cycle
Parameter
Symbol
min.
max.
Write to pre-charge command delay (same bank)
tWPD
3 + BL/2
Read to pre-charge command delay (same bank)
tRPD
BL/2
Write to read command delay (to input all data)
Burst stop command to write command delay
(CL = 3)
(CL = 3.5)
Burst stop command to DQ High-Z
(CL = 3)
(CL = 3.5)
Read command to write command delay (to output all data)
(CL = 3)
(CL = 3.5)
Pre-charge command to High-Z
(CL = 3)
(CL = 3.5)
tWRD
2 + BL/2
tBSTW
2
tBSTW
3
tBSTZ
3
tBSTZ
3.5
tRWD
2 + BL/2
tRWD
3 + BL/2
tHZP
3
tHZP
3.5
Write command to data in latency
tWCD
2
Write recovery
tWR
1
Register set command to active or register set command
tMRD
2
Self refresh exit to non-read command
tSNR
10
Self refresh exit to read command
tSRD
200
Power down entry
tPDEN
1
Power down exit to command input
tPDEX
1
CKE minimum pulse width
tCKEPW
1
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| HB54R1G9F2-B75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM |
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| HB54R1G9F2U-A75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM |
| HB54R1G9F2U-B75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR SDRAM DIMM |
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