參數(shù)資料
型號(hào)： HB52R1289E22-B6B
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 1 GB Registered SDRAM DIMM 1 GB Registered SDRAM DIMM (36 pcs of 64 M 】 4 Components) PC100 SDRAM
中文描述： 128M X 72 SYNCHRONOUS DRAM MODULE, 7.5 ns, DMA168
封裝： DIMM-168
文件頁(yè)數(shù)： 16/18頁(yè)
文件大?。?/td> 168K
代理商： HB52R1289E22-B6B
HB52R1289E22-A6B/B6B
Data Sheet E0017H20
16
Pin Functions
CK0 to CK3 (input pin):
CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0
to
S3
(input pin):
When
S
is Low, the command input cycle becomes valid. When
S
is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE
,
CE
and
W
(input pins):
Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins):
Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY9, AY11) is determined by A0 to A9, A11 level
at the read or write command cycle CK rising edge. And this column address becomes burst access start
address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are
precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by
BA0/BA1 (BA) is precharged.
BA0/BA1 (input pin):
BA0/BA1 are bank select signal (BA). The memory array is divided into bank 0,
bank 1, bank 2 and bank 3. If BA0 is Low and BA1 is Low, bank 0 is selected. If BA0 is High and BA1 is
Low, bank 1 is selected. If BA0 is Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is
High, bank 3 is selected.
CKE0 (input pin):
This pin determines whether or not the next CK is valid. If CKE is High, the next CK
rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and
clock suspend modes.
DQMB0 to DQMB7 (input pins):
Read operation: If DQMB is High, the output buffer becomes High-Z. If
the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written.
DQ0 to DQ63, CB0 to CB7 (input/output pins):
Data is input to and output from these pins.
V
CC
(power supply pins):
3.3 V is applied.
V
SS
(power supply pins):
Ground is connected.
REGE (input pins):
If REGE is High, the register is
″
registered
″
mode. If REGE is Low, the register is
″
buffered
″
mode.
Detailed Operaion Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet (E0082H).
相關(guān)PDF資料
PDF描述
HB52R1289E22 1 GB Registered SDRAM DIMM(1GB 寄存同步DRAM DIMM)
HB52R168DB 128 MB Unbuffered SDRAM S.O.DIMM(128 MB 未緩沖同步DRAM S.O.DIMM)
HB52R2569E2 2 GB Registered SDRAM DIMM(2GB 寄存同步DRAM DIMM)
HB52R329E22 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM)
HB52R329E2 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HB52R1289E2-A6A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x72 SDRAM Module
HB52R1289E2-B6A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x72 SDRAM Module
HB52R1289E2U-A6B 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC100 SDRAM
HB52R1289E2U-B6B 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC100 SDRAM
HB52R168DB-10 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x64 SDRAM Module
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*