參數(shù)資料
型號(hào)： GS9092-CNE3
廠商： Gennum Corporation
英文描述： GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI
中文描述： GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi)
文件頁數(shù)： 7/58頁
文件大?。?/td> 608K
代理商： GS9092-CNE3
GS9092 Data Sheet
28202 - 2
September 2005
7 of 58
12
IOPROC_EN
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal Levels are LVCMOS / LVTTL compatible.
Used to enable or disable the I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
SMPTE 352M Payload Identifier Packet Generation and Insertion
Illegal Code Remapping
EDH Generation and Insertion
Ancillary Data Checksum Insertion
TRS Generation and Insertion
To enable a subset of these features, keep the IOPROC_EN pin HIGH
and disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When this pin is set LOW, the device will enter low-latency mode.
NOTE: When the internal FIFO is configured for video mode or ancillary
data insertion mode, the IOPROC_EN pin must be set HIGH.
13
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI
are configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI
are configured as GSPI pins for normal host interface operation.
14
RESET
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to reset the internal operating conditions to default setting or to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW):
When asserted LOW, all functional blocks will be set to default
conditions ,SDO and SDO are muted, and all input signals become high
impedance with the exception of the STAT pins which will be driven
LOW.
When set HIGH, normal operation of the device resumes 10usec after
the LOW-to-HIGH transition of the RESET signal.
JTAG Test Mode (JTAG/HOST = HIGH):
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
NOTE: For power on reset requirements please see
Device Power Up
on page 54
.
15, 45
CORE_VDD
Non
Synchronous
Input
Power
Power supply for digital logic blocks. Connect to +1.8V DC.
NOTE: For power sequencing requirements please see
Device Power
Up on page 54
.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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