參數(shù)資料
型號(hào)： GS9092-CNE3
廠商： Gennum Corporation
英文描述： GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI
中文描述： GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi)
文件頁(yè)數(shù)： 24/58頁(yè)
文件大?。?/td> 608K
代理商： GS9092-CNE3
GS9092 Data Sheet
28202 - 2
September 2005
24 of 58
The application layer must start writing the first active pixel of the line into location
zero of memory. Therefore, the user should use the WR_RESET pin to reset the
FIFO write pointer prior to writing to the device.
NOTE: The BLANK signal must not be asserted in video mode.
3.3.2 DVB-ASI Mode
The internal FIFO is in DVB-ASI mode when the application layer sets the
FIFO_EN pin HIGH and the FIFO_MODE[1:0] bits in the IOPROC_DISABLE
register are configured to 01b. By default, the FIFO_MODE[1:0] bits are set to 01b
by the device whenever the DVB_ASI pin is set HIGH (i.e. the device is in DVB-ASI
mode); however, the application layer may program the FIFO_MODE[1:0] bits as
required.
Figure 3-3
shows the input and output signals of the FIFO when it is configured for
DVB-ASI Mode.
Figure 3-3: FIFO in DVB-ASI Mode
When operating in DVB-ASI mode, the GS9092's FIFO can be used for clock rate
interchange operation. 8-bit MPEG data as well as a K_IN control signal must be
written to the FIFO by the application layer. The MPEG data and control signal can
be simultaneously clocked into the FIFO at any rate using the rising edge of the
WR_CLK pin.
The 8-bit MPEG data stream may consist of only MPEG packets, or both MPEG
packets and special characters (such as the K28.5 stuffing characters). The
application layer must set K_IN HIGH whenever a special character is present in
the data stream, otherwise it should be LOW. The GS9092 uses the K_IN signal to
determine whether or not a given byte in the FIFO is an MPEG packet that needs
8b/10b encoded.
The INSSYNCIN pin should be grounded while operating the FIFO in DVB-ASI
mode.
The GS9092 internally reads the data out of the FIFO at the PCLK rate and adds
the necessary number of stuffing characters based on the FIFO status flags.
WR_CLK
K_IN
FIFO
(DVB-ASI Mode)
RD_CLK (PCLK)
Internal
Application Interface
8-bit MPEG Data
FIFO_FULL
FIFO_EMPTY
8-bit MPEG Data
K_IN
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