參數(shù)資料
型號: GS882V37BB
廠商: GSI TECHNOLOGY
英文描述: 256K x 36 9Mb SCD/DCD Sync Burst SRAM
中文描述: 256K × 36 9Mb以上SCD的/雙氰胺同步突發(fā)靜態(tài)存儲器
文件頁數(shù): 6/27頁
文件大小: 727K
代理商: GS882V37BB
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Activate DQPx I/Os (x18/x36
mode)
Deactivate DQPx I/Os (x16/x32
mode)
Power Down Control
ZZ
L or NC
H
Single/Dual Cycle Deselect Control
SCD
L
H or NC
L
H or NC
FLXDrive Output Impedance Control
ZQ
9th Bit Enable
PE
L
H or NC
GS882V37BB/D-360/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 3/2005
6/27
2003, GSI Technology
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18
相關(guān)PDF資料
PDF描述
GS882Z18AB 9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS882Z18AB-133 9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS882Z18AB-133I 9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS882Z18AB-150 9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS882Z18AB-150I 9Mb Pipelined and Flow Through Synchronous NBT SRAM
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