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參數(shù)資料
| 型號： | GS8330DW72C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 26/30頁 |
| 文件大小： | 583K |
| 代理商： | GS8330DW72C |
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Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
26/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
JTAG TAP Instruction Set Summary
JTAG Port Recommended Operating Conditions and DC Characteristics
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z/
PRELOAD
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all Data and Clock output drivers to High-Z.
1
Private
011
Private instruction.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
1
Private
101
Private instruction.
1
Private
110
Private instruction.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in Test-Logic-Reset state.
Parameter
Symbol
Min.
Max.
Unit
Notes
Test Port Input High Voltage
V
IHT
0.65 * V
DD
V
DD
+0.3
V
1
Test Port Input Low Voltage
V
ILT
–0.3
0.35 * V
DD
V
1
TMS, TCK and TDI Input Leakage Current
I
INTH
–2
2
uA
2
TMS, TCK and TDI Input Leakage Current
I
INTL
–50
2
uA
3
TDO Output Leakage Current
I
OLT
–2
2
uA
4
Test Port Output High Voltage
V
OHT
V
DD
– 100 mV
—
V
5, 6
Test Port Output Low Voltage
V
OLT
—
100 mV
V
7
Notes:
1.
2.
3.
4.
5.
6.
7.
Input Under/overshoot voltage must be –1 V < Vi < V
DD
+ 1 V with a pulse width not to exceed 20% tTKC.
V
DD
≥
V
IN
≥
V
IL
0 V
≤
V
IN
≤
V
IL
Output Disable, V
OUT
= 0 to V
DDI
The TDO output driver is served by the V
DDQ
supply.
I
OH
= –100 uA
I
OL
= +100 uA
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