參數(shù)資料
型號(hào)： GS8330DW72C
廠商： Electronic Theatre Controls, Inc.
元件分類： DC/DC變換器
英文描述： 1 watt dc-dc converters
中文描述： 1瓦的DC - DC轉(zhuǎn)換器
文件頁(yè)數(shù)： 24/30頁(yè)
文件大小： 583K
代理商： GS8330DW72C
Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
24/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state, the Instruction Register is placed between TDI and TDO. In this state the
desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all
instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP
instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Some Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified
in the BSDL file. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O
ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAP’s input
data capture set-up plus hold time (tTS plus tTH ). The RAM’s clock inputs need not be paused for any other TAP operation except capturing
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
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