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參數(shù)資料
| 型號(hào)： | GS8330DW72C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 11/30頁(yè) |
| 文件大?。?/td> | 583K |
| 代理商： | GS8330DW72C |
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Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
11/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read
operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle
in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2
would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.
Echo Clock Control in Two Banks of SigmaRAMs
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
QD
CQ
Bank 1
CQ
Bank 2
DQ
Bank 2
QB
CQ1 + CQ2
QC
Address
A
B
/E
1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
QA
ADV
F
D
E
C
Read
Read
Read
CK
Read
Read
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